SONG Yu-kun, QU Shuang-shuang, XU Li-han, et al. Design and implementation of mixed radix reconfigurable Fast Fourier Transform processor[J]. 2020, 37(1): 87-92.
SONG Yu-kun, QU Shuang-shuang, XU Li-han, et al. Design and implementation of mixed radix reconfigurable Fast Fourier Transform processor[J]. 2020, 37(1): 87-92.DOI:
Design and implementation of mixed radix reconfigurable Fast Fourier Transform processor
This paper presents a novel mixed radix reconfigurable FFT processor
which consists of a new reconfigurable butterfly unit supporting radix-2/3 FFT and multi-channel parallel collision-free memory
which implements multi-channel data parallelism and the continuity of the operation for FFT operation. The maximum frequency of this design is 1.06 GHz under the TSMC28nm process. At the same time
the mixed radix FFT processor hardware test system based on the Xilinxs XC7V2000T FPGA chip completes performance verification. The results shows that the design supports FFT operations for radix-2 mode
radix-3 mode and radix-2/3 mixed mode
and the execution speed reaches the theoretical period value under the given number of butterfly multipliers. For single-precision floating-point numbers
mixed radix FFT processor provides a result accuracy of 10.
关键词
Keywords
references
SHI X Y, LIU Y Q, CHOU H R. 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches[J]. IEEE Transactions On Circuits And Systems-I: Regular Papers, 2017, 64(4): 1456 - 1467.DOI:10.1109/TCSI.2017.2654451.
SUZUKIY, SONET, KIDOKI. New FFT algorithm of radix-3, 6, AND 12[J]. IEEE Transactions on Acoustics, Speech and Signal Processing, 1986, 34(2): 380-383. DOI: 380
BHAGAT D, MERGLER H W. A high-performance microprocessor-based FFT processor[J]. IEEE Trans. Very Large Scale Integration. (VLSI) Syst., 2016, 24(9):3008-3012. DOI: 3008
LUZ A G DA, COSTA E A DA, GHISSONI S. Reducing power consumption in FFT architectures by using heuristic-based algorithms for the ordering of the twiddle factors[C]//Proc. IEEE 3rd Latin Amer. Symp. Circuits Syst.(LASCAS) 2012, [S.L].2012: 1-4.
HUANG S J, CHEN S.A high-throughput radix-16 FFT processor with parallel and normal input/output ordering for IEEE 802.15.3c systems[J]. IEEE Transactions on Circuits and System I: Regular Papers, 2012, 59(8):1752-1765. DOI: 1752
JONEWOOK S, EARL E. Improved architectures for a floating-point fused dot product unit[C]//IEEE Symposium on Computer Arithmetic, Austin. USA, 2013: 41-48.
ABER M A, MASSICOTTE D.A new FFT concept for efficient VLSI implementation: Part Ⅰ-Butterfly processing element[C]//16th International Conference on Digital Signal Processing. Santorini-Hellas, 2009.