Design of wide-band continuous-time sigma-delta modulator based on matlab

WANG Meng-hao; HOU Xun-ping; LU Tie-jun

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Design of wide-band continuous-time sigma-delta modulator based on matlab

更新时间：2026-09-04

- Design of wide-band continuous-time sigma-delta modulator based on matlab
- Vol. 37, Issue 6, Pages: 70-74(2020)
- 作者机构：
  
  北京微电子技术研究所,北京,100071
- 作者简介：
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- Published：2020
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王盟皓, 侯训平, 陆铁军. 基于Matlab的宽带连续时间Sigma-Delta调制器设计[J]. 微电子学与计算机, 2020, 37(6): 70-74.

WANG Meng-hao, HOU Xun-ping, LU Tie-jun. Design of wide-band continuous-time sigma-delta modulator based on matlab[J]. 2020, 37(6): 70-74.
王盟皓, 侯训平, 陆铁军. 基于Matlab的宽带连续时间Sigma-Delta调制器设计[J]. 微电子学与计算机, 2020, 37(6): 70-74. DOI：

WANG Meng-hao, HOU Xun-ping, LU Tie-jun. Design of wide-band continuous-time sigma-delta modulator based on matlab[J]. 2020, 37(6): 70-74. DOI：

摘要

本文利用Matlab集成工具箱设计了一款单环三阶三位连续时间Sigma-Delta调制器.与离散时间调制器相比，连续时间调制器虽然对非理想因素较为敏感，但其在功耗、带宽方面却有着突出的表现.本文在设计过程中，加入了零阶反馈环路对额外环路延时进行吸收，并对连续时间调制器最主要的三种非理想特性进行了分析.最终基于65 nm CMOS工艺，设计电路并完成版图，通过spectre仿真，本文设计的调制器在10 MHz带宽下，可以达到78.20 dB的信噪失真比，且功耗仅为5.39 mW.

Abstract

This paper presents a single-loop 3rd-order 4-bit Continuous-Time Sigma-Delta modulator using the Matlab toolbox. Compared with Discrete-Time modulators

continuous-time modulators are sensitive to non-ideal factors

but they have outstanding performance in terms of power consumption and bandwidth. In the design process

a zero-order feedback loop is added to absorb the excess loop delay

and the three main non-ideal factors of the continuous-time modulator are analyzed. Finally

based on the 65nm CMOS process

the circuit and layout of the modulator is completed. Through spectre simulation

the modulator can achieve 78.20dB signal to noise and distortion ratio with bandwidth of 10MHz

while the power consumption is only 5.39mW.

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references

ALEXANDER E, LIU Q Y, CARLOS B, et al.A 43-mW MASH 2-2 CTΣΔModulator Attaining 74.4/75.8/76.8dB of SNDR/SNR/DR and 50MHz of BW in 40-nm CMOS[J]. IEEE J. Solid-State Circuits, 2017, 52(2): 448-459. DOI: 448

RUDOLF R, JOHN G, JOACHIM B, et al.A 10MHz Bandwidth, 70dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection[J], IEEE J. Solid-State Circuits, 2016, 51(3):660-670. DOI: 660

CHERRY J, SNELGROVE W. Clock jitter and quantizer metastability in continuous-time delta-sigma modulators[J]. IEEE Transactions on Circuits and SystemⅡ:Analog and Digital Signal Processing, 1999, 46(6):661-676. DOI: 661

CHEN Y H, CONG L, CHI LL, et al.A4.5mW CT Self-Coupled ΔΣModulator with 2.2MHz BW and 90.4dB SNDR Using Residual ELD Compensation[C]// IEEE International Solid-State Circuits Conference. San Francisco, 2015: 274-275.

WU S H, KAO T K, LEE Z M, et al.A 160MHz-BW 72dB-DR 40mW Continuous-Time ΔΣ Modulator in 16nm CMOS with Analog ISI-Reduction Technique[C]// IEEE International Solid-State Circuits Conference. San Francisco, 2016: 280-281.

CHERRY J, SNELGROVE W.Excess loop delay in continuous-time delta-sigma modulators[J]. IEEE Transactions on Circuits and System Ⅱ:Analog and Digital Signal Processing, 1999, 46(4):376-389. DOI: 376

ORTMANSM, GERFERS F, MANOLI Y, et al.Influence of finite integrator gain bandwidth on continuous-time sigmadelta modulators[C]//IEEE InternationalSymposium onCircuits and Systems.Bangkok, IEEE, 2003: 925-928.

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