A buffer address scheduling method for general CNN accelerator

WU Lei; WEI Zi-han; ZHANG Wei-gong; WANG Jing; GAO Lan

Chinese

您当前的位置：

首页 >

文章列表页 >

A buffer address scheduling method for general CNN accelerator

更新时间：2026-09-04

- A buffer address scheduling method for general CNN accelerator
- Vol. 37, Issue 7, Pages: 82-86(2020)
- 作者机构：
  
  1. 首都师范大学机构信息工程学院,北京,102248
  2. 电子系统可靠性技术北京市重点实验室机构,北京,100048
  3. 西安电子科技大学电子工程学院,陕西,西安,710126
  4. 北京成像理论与技术高精尖创新中心,北京,100048
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
移动端阅览
武磊, 魏子涵, 张伟功, 王晶, 高岚. 一种通用CNN加速器的缓冲区地址调度方法[J]. 微电子学与计算机, 2020, 37(7): 82-86.

WU Lei, WEI Zi-han, ZHANG Wei-gong, et al. A buffer address scheduling method for general CNN accelerator[J]. 2020, 37(7): 82-86.
武磊, 魏子涵, 张伟功, 王晶, 高岚. 一种通用CNN加速器的缓冲区地址调度方法[J]. 微电子学与计算机, 2020, 37(7): 82-86. DOI：

WU Lei, WEI Zi-han, ZHANG Wei-gong, et al. A buffer address scheduling method for general CNN accelerator[J]. 2020, 37(7): 82-86. DOI：

摘要

针对由神经网络参数多计算复杂度高导致的数据访问灵活性不足问题，本文提出了一种通用CNN加速器的缓冲区地址调度方法.通过在地址控制器中灵活调度片上缓存，卷积层均能由一个或两个特定卷积运算单元实现，降低资源开销；通过输入参数可配置不同大小的图像及卷积核，具有一定的通用性.实验结果表明，该地址调度方法能够适用于不同数目及尺寸的卷积、池化和全连接操作，并且计算性能有所提高.

Abstract

Aiming at the problem of data access conflicts caused by multiple neural network parameters and high computational complexity

this paper proposes a buffer address scheduling method for general CNN accelerator. The on-chip buffer is flexibly scheduled in the address controller

and the convolutional layers can be implemented by one or two specific convolutional operation units to reduce resource consumption; the input parameters can be configured with images and convolution kernels of different sizes

with some universality. The experimental results show that the address scheduling method can be applied to different numbers and sizes of convolution

pooling and full connection operations

and the computing performance is improved.

关键词

Keywords

references

RAJARAMAN S, CANDEMIR S, KIM I, et al. Visualization and Interpretation of Convolutional Neural Network Predictions in Detecting Pneumonia in Pediatric Chest Radiographs[J]. Applied Sciences, 2018, 8(10):1715. DOI: 1715

ZHOU Y, JIANG J. An FPGA-based accelerator implementation for deep convolutional neural networks[C]// International Conference on Computer Science and Network Technology. Changchun, China, IEEE, 2016: 829-832.

CHEN Y, LUO T.DaDianNao: A machine-learning supercomputer[C]// The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). Cambridge, United Kingdom, IEEE, 2014: 609-622.

MA Y, CAO Y, VRUDHULA S, et al. Optimizing the convolution operation to accelerate deep neural networks on FPGA[J]. IEEE Transactions on Very Large Scale Integration Systems, 2018, 26(7): 1354-1367. DOI: 1354

CHEN Y H, KRISHNA T, EMER J S, et al. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks[C]// IEEE International Solid State Circuits Conference.San Francisco, CA, USA, IEEE, 2016: 262-263.

KRIZHEVSKY A, SUTSKEVER I, HINTON G. ImageNet classification with deep convolutional neural networks[C]// International Conference on Neural Information Processing Systems. Curran Associates Inc.2012: 1097-1105.

ALWANI M, CHEN H, FERDMAN M, et al.Fused-layer CNN accelerators[C]// The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). Taipei, Taiwan, IEEE, 2016: 1-12.

ZHANG J, LI J. Improving the performance of Open CL-based FPGA accelerator for convolutional neural network[C]// Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Monterey, CA, USA, ACM, 2017: 25-34.

卢冶, 陈瑶, 李涛, 等.面向边缘计算的嵌入式FPGA卷积神经网络构建方法[J].计算机研究与发展, 2018, 55(3):551-562. DOI: 551

余子健, 马德, 严晓浪, 等.基于FPGA的卷积神经网络加速器[J].计算机工程, 2017, 43(1): 109-114. DOI: 109

翟社平, 邱程, 杨媛媛, 等.基于FPGA的卷积神经网络加速器设计与实现[J].微电子学与计算机, 2019, 36(8):83-86. DOI: 83

方荣强, 王晶, 姚治成, 等.多层神经网络算法的计算特征建模方法[J].计算机研究与发展, 2019, 56(6):1170-1181. DOI: 1170

王巍, 周凯利, 王伊昌, 等.卷积神经网络(CNN)算法的FPGA并行结构设计[J].微电子学与计算机, 2019, 36(4):57-62. DOI: 57

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

A spherical perception-based panoramic image saliency prediction algorithm with longitude weighting

CNN inference task division and memory scheduling algorithm based on tiling subgraph

Design of PCNN_LSTM hardware accelerator for SOC estimation of lithium batteries

Research on SAR image denoising technology based on U-Net network structure

Dynamic gesture recognition based on lightweight (2+1)D convolution structure

Related Author

CHEN Ziyi

LU Chenglong

LAN Hong

CHEN Song

GE Mengke

WANG Junpeng

CHENG Ran

WU Hao

Related Institution

School of Information Engineering, Jiangxi University of Science and Technology

School of Microelectronics, University of Science and Technology of China

Institute of Artificial Intelligence, Hefei Comprehensive National Science Center

School of Computer Science and Technology, Anhui University

College of Electronics Engineering/International Semiconductor College, Chongqing University of Posts and Telecommunications

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰