A new stage for microsystem integration-the integrated development of integrated circuits chips and system-level electronic packaging

MIAO Min; JIN Yu-feng

Chinese

您当前的位置：

首页 >

文章列表页 >

A new stage for microsystem integration-the integrated development of integrated circuits chips and system-level electronic packaging

更新时间：2026-09-04

- A new stage for microsystem integration-the integrated development of integrated circuits chips and system-level electronic packaging
- Vol. 38, Issue 1, Pages: 1-6(2021)
- 作者机构：
  
  1. 北京信息科技大学机构信息微系统研究所,北京,100101
  2. 北京大学深圳研究生院,深圳,518055
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2021
- 稿件说明：
移动端阅览
缪旻, 金玉丰. 微系统集成全新阶段——IC芯片与电子集成封装的融合发展[J]. 微电子学与计算机, 2021, 38(1): 1-6.

MIAO Min, JIN Yu-feng. A new stage for microsystem integration-the integrated development of integrated circuits chips and system-level electronic packaging[J]. 2021, 38(1): 1-6.
缪旻, 金玉丰. 微系统集成全新阶段——IC芯片与电子集成封装的融合发展[J]. 微电子学与计算机, 2021, 38(1): 1-6. DOI：

MIAO Min, JIN Yu-feng. A new stage for microsystem integration-the integrated development of integrated circuits chips and system-level electronic packaging[J]. 2021, 38(1): 1-6. DOI：

摘要

拓展摩尔定律已成为集成电路及电子信息通信硬件产业的重大战略之一

其中微系统技术发展进入全新阶段

集成电路芯片与集成封装组件的界限日渐模糊

形成了融合发展的新局面

正对微系统异质集成技术领域发展产生深远影响.结合团队科研实践

本文从架构演进、芯片-封装一体化设计策略、多物理域协同分析与优化、集成平台的重大创新等层面

分析IC与集成封装融合发展阶段的技术特征、内涵与动向

并对未来应用前景、发展路径进行展望.

Abstract

"More than Moore" has become the preferred strategy for integrated circuit and electronic

information and telecommunication hardware industries and therefore has just promoted microsystem technology onto a new stage

whereon the boundary between IC (integrated circuit) chips and system-level electronic package has become increasingly blurred

triggering a fashion of integrated development of two domain. This new stage is now exerting a far-reaching influence on the development of microsystem heterogeneous integration domain. Consequently

based on the personal scientific research practice

the characteristics

connotations and trends are analyzed and inferred in-depth for this whole new IC-package co-development stage

from the perspective of architecture evolution

chip-package co-design strategy

multi-physics co-analysis and co-optimization

and major technical innovations in integrated assembling and manufacturing; in addition

the future applications are prospected and the path of evolution is suggested.

关键词

Keywords

references

VIVET P, GUTHMULLER E, THONNART Y, et al. A 220GOPS 96-core processor with 6 chiplets 3D-stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-chiplet interconnects and 156mW/mm2@ 82%-Peak-efficiency DC-DC converters[C]//2020 IEEE International Solid-State Circuits Conference-(ISSCC). San Francisco, CA, USA, USA: IEEE, 2020: 46-47.

GREENHILL D, HO R, LEWIS D, et al. 3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration[C]//2017 IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, USA: IEEE, 2017: 54-55.

PARES G, JEAN-PHILIPPE M, EDOUARD D, et al. Highly compact RF transceiver module using high resistive silicon interposer with embedded inductors and heterogeneous dies integration[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC). Las Vegas, NV, USA, USA: IEEE, 2019: 1279-1286.

MA S L, CHAI Y, YAN J, et al. A 2.5D integrated L band Receiver based on High resistivity Si interposer[C]//2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). Beijing, China: IEEE, 2018: 74-77.

WALDROP M M. The chips are down for Moore's law[J]. Nature, 2016, 530(7589): 144-147. DOI: 10.1038/530 144a.

Cambridge CHROSTOWSKI L, HOCHBERG M. Silicon photonics design: from devices to systems[M]. Cambridge: Cambridge University Press, 2015.

BECK N, WHITE S, PARASCHOU M, et al. 'Zeppelin': An SoC for multichip architectures[C]//2018 IEEE International Solid-State Circuits Conference-(ISSCC). San Francisco, CA, USA: IEEE, 2018: 40-42.

WU T T, SHEN C H, SHIEH J M, et al. Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for internet of things[C]//2015 IEEE International Electron Devices Meeting (IEDM). Washington, DC, USA: IEEE, 2015: 640-643.

LIN M S, HUANG T C, TSAI C C, et al. A 7nm 4GHz Arm-core-based CoWoS chiplet design for high performance computing[C]//2019 Symposium on VLSI Circuits. Kyoto, Japan: IEEE, 2019: C28-C29.

许居衍.复归于道--封装改道芯片业(演讲记录稿)[J].电子与封装, 20 19, 19( 10): 1-3. DOI: 10. 16257/j.cnki. 168 1- 1070.20 19. 100 1. XU J Y.Back to the Origin-Packaging are Changing the Path of IC Industry: a Transcript for the Keynote Speech[J]. Electronics % Packaging, 20 19, 19( 10): 1-3. DOI: 10. 16257/j.cnki. 168 1- 1070.20 19. 100 1.

COUDRAIN P, CHARBONNIER J, GARNIER A, et al. Active interposer technology for chiplet-based advanced 3D system architectures[C]//2019 69th Electronic Components and Technology Conference (ECTC). Las Vegas, NV, USA, USA: IEEE, 2019: 568-578.

Views

349

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Research on assembly action recognition based on MSS-YOLO-MPHands fusion architecture

Steganography model guided by attention mechanism and improved dense convolution

Implementation and verification of a dual-chain power gating strategy for low power design

Aerial small object detection algorithm based on improved RT-DETR

Microservices anomaly detection based on the correlation of monitoring metrics

Related Author

No data

Related Institution

No data

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰