SRAM FPGA single event fault injection based on SEM IP and partial reconfiguration

WANG Mengru; ZHOU Shan; XUE Panpan; KONG Lu; WANG Jinbo

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SRAM FPGA single event fault injection based on SEM IP and partial reconfiguration

更新时间：2026-09-04

- SRAM FPGA single event fault injection based on SEM IP and partial reconfiguration
- Vol. 38, Issue 8, Pages: 8-12(2021)
- 作者机构：
  
  1. 中国科学院大学机构,北京,101408
  2. 中国科学院机构空间应用工程与技术中心,北京,100094
- 作者简介：
- 基金信息：
- DOI：
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- Published：2021
- 稿件说明：
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王梦茹, 周珊, 薛盼盼, 孔璐, 王金波. 基于SEM IP和部分重配置的SRAM型FPGA单粒子故障注入[J]. 微电子学与计算机, 2021, 38(8): 8-12.

WANG Mengru, ZHOU Shan, XUE Panpan, et al. SRAM FPGA single event fault injection based on SEM IP and partial reconfiguration[J]. 2021, 38(8): 8-12.
王梦茹, 周珊, 薛盼盼, 孔璐, 王金波. 基于SEM IP和部分重配置的SRAM型FPGA单粒子故障注入[J]. 微电子学与计算机, 2021, 38(8): 8-12. DOI：

WANG Mengru, ZHOU Shan, XUE Panpan, et al. SRAM FPGA single event fault injection based on SEM IP and partial reconfiguration[J]. 2021, 38(8): 8-12. DOI：

摘要

SEM IP(Soft Error Mitigation软错误缓解核)是对SRAM FPGA设计进行单粒子故障注入的一种有效方法.然而由于目标设计与SEM IP部分随机布局布线在一块芯片上，导致进行故障注入时很有可能会打翻SEM IP所使用的配置寄存器而导致故障注入停止工作，同时对于目标设计失效率统计不准确.为解决这一问题，基于SEM IP和部分重配置技术开发了一套单粒子故障注入原型系统用于单粒子故障注入实验.该方法将SEM IP和目标设计布局布线到芯片的不同区域，能够只对目标设计所在区域进行故障注入并且不中断目标设计运行，并且在发生不可纠正错误后对目标设计所在区域进行部分重新配置，配置数据更少，用时更短，系统故障的注入效率大大提高，提高对于目标设计软错误失效率估计的准确性.

Abstract

SEM(Soft Error Mitigation)IP is an effective method of single event fault injection for SRAM FPGA design. However

the target design and the SEM IP part are randomly placed and routed on the same chip

when fault injection is performed

the configuration register used by the SEM IP is likely to be overturned

causing the fault injection system to stop working and the failure rate of the target design is not accurate. To solve this problem

a single event fault injection prototype system based on SEM IP and partial reconfiguration technology is developed for single particle injection. The method places and routes the SEM IP and the target design to different areas of the chip

can only perform fault injection into the area where the target design is located without interrupting SEM IP operation itself. Besides

the area of the target design can be reconfigured when an uncorrectable error occurs. The method needs less configuration data and shorter time

which greatly improves the efficiency of fault injection experiment and the accuracy of the target design soft failure rate estimation.

关键词

Keywords

references

Beijing 何宾. Xilinx FPGA权威设计指南[M]. 北京: 电子工业出版社, 2018. HE B. Xilinx FPGA Definitive Design Guide[M]. Beijing: Electronic Industry Press, 2018.

EL-ARABY E, GONZALEZ I, EL-HAZAWI T. Exploiting partial run-time reconfiguration for high-performance reconfigurable computing[J]. ACM Transactions on Reconfigurable Technology and Systems, 2009, 1(4): Article No. : 21. DOI: 10.1145/1462586.1462590.

SCALERA S M, VAZQUEZ J R. The design and implementation of a context switching FPGA[C]//IEEE Symposium on FPGAs for Custom Computing Machines. Napa Valley, CA, USA: IEEE, 1998: 78-85. DOI: 10.1109/FPGA.1998.707884.

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