Code compression technology for processors based on RISC-V instruction set architecture

CHENG Zhan-tao; LIANG Feng; ZHANG Guo-he

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Code compression technology for processors based on RISC-V instruction set architecture

更新时间：2026-09-04

- Code compression technology for processors based on RISC-V instruction set architecture
- Vol. 38, Issue 6, Pages: 13-19(2021)
- 作者机构：
  
  西安交通大学微电子学院,陕西,西安,710049
- 作者简介：
- 基金信息：
- DOI：
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- Published：2021
- 稿件说明：
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程战涛, 梁峰, 张国和. 面向RISC-V指令集架构处理器的代码压缩技术[J]. 微电子学与计算机, 2021, 38(6): 13-19.

CHENG Zhan-tao, LIANG Feng, ZHANG Guo-he. Code compression technology for processors based on RISC-V instruction set architecture[J]. 2021, 38(6): 13-19.
程战涛, 梁峰, 张国和. 面向RISC-V指令集架构处理器的代码压缩技术[J]. 微电子学与计算机, 2021, 38(6): 13-19. DOI：

CHENG Zhan-tao, LIANG Feng, ZHANG Guo-he. Code compression technology for processors based on RISC-V instruction set architecture[J]. 2021, 38(6): 13-19. DOI：

摘要

针对嵌入式系统处理器代码量指数式增长带来的设计与验证难题，提出一种适用于RISC-V指令集架构处理器的Bitmask代码压缩技术.结合RISC-V指令集特点，设计了混合编码与分离字典相结合的Bitmask代码压缩算法; 在不影响处理器结构和Cache工作机制的基础上，设计精简的硬件解压缩单元，减小了嵌入式系统处理器所需的程序内存空间.采用面向RISC-V指令集的混合编码压缩指令格式，减小原始指令码的码字长度，改善了代码压缩率; 采用分离的两个字典结构，在不影响代码压缩率的前提下，减小了硬件解压缩延迟.结果表明，在RISC-V指令集架构上不增加过多硬件开销的情况下，代码压缩率平均为61.1%，大大减小了处理器所需的程序内存空间.

Abstract

Aiming at design and verification problems caused by the exponential growth of the code size in the embedded system processors

the Bitmask-based code compression technology for processors based on RISC-V instruction set architecture is presented. Based on the features of RISC-V instruction set

a Bitmask-based code compression algorithm combined with mixed encoding and separate dictionary is designed. Without affecting the processor structure and Cache working mechanism

a simple and efficient hardware decompression unit is designed to reduce the program memory space required by the embedded system processor. Mixed encoding format for RISC-V instruction set is used to reduce the length of the original instruction

which improves the code compression rate. Besides

two separated dictionaries are used to obtain a small hardware decompression delay without affecting the code compression rate. The experimental results show that the code compression ratio is 61.1% on average without much hardware overhead on the RISC-V instruction set architecture

which greatly reduces the program memory space required by the processor.

关键词

Keywords

references

洪兴勇. 高性能BWDSP处理器指令Cache研究与设计[D]. 合肥: 合肥工业大学, 2013: 55-56. HONG X Y. The research and design of high performance BWDSP processor instruction Cache[D]. Hefei: Hefei University of Technology, 2013: 55-56.

WOLFE A, CHANIN A. Executing compressed programs on an embedded RISC architecture[C]//Proceedings of the 25th Annual International Symposium on Microarchitecture. Portland, USA: IEEE, 1992: 81-91. DOI: 10.1109/MICRO.1992.697002.

WATERMAN A, LEE Y, PATTERSON D A, et al. The RISC-V instruction set manual, volume I: User-level ISA, version 2.1[R]. Berkeley, CA: University of California, 2016.

WANG W J, LIN C H. An improved BitMask based code compression algorithm for embedded systems[C]//Proceedings of 2011 International Symposium on Electronic System Design. Kochi, India: IEEE, 2011: 152-157. DOI: 10.1109/ISED.2011.15.

QIN X K, MUTHRY C, MISHRA P. Decoding-aware compression of FPGA bitstreams[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(3): 411-419. DOI: 10.1109/TVLSI.2009.2035704.

阳晔. 面向嵌入式处理器的代码压缩研究[D]. 杭州: 浙江大学, 2007: 17-18. YANG Y. Research on code compression for embedded processors[D]. Hangzhou: Zhejiang University, 2007: 17-18.

LEFURGY C, BIRD P, CHEN I C, et al. Improving code density using compression techniques[C]//Proceedings of the 30th Annual International Symposium on Microarchitecture. Research Triangle Park, USA: IEEE, 1997: 194-203. DOI: 10.1109/MICRO.1997.645810.

SEONG S W, MISHRA P. A bitmask-based code compression technique for embedded systems[C]//Proceedings of 2006 IEEE/ACM International Conference on Computer Aided Design. San Jose: IEEE, 2006: 251-254. DOI: 10.1109/ICCAD.2006.320144.

WANG W J, LIN C H. Code compression for embedded systems using separated dictionaries[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(1): 266-275. DOI: 266

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