Towards ReRAM-based Accelerator: An Energy-efficient NN Model Compression Framework

SHEN Linyao; WANG Qin; JIANG Jianfei; JING Naifeng

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Towards ReRAM-based Accelerator: An Energy-efficient NN Model Compression Framework

更新时间：2026-09-04

- Towards ReRAM-based Accelerator: An Energy-efficient NN Model Compression Framework
- Vol. 38, Issue 8, Pages: 20-27(2021)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
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- DOI：
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- Published：2021
- 稿件说明：
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沈林耀, 王琴, 蒋剑飞, 景乃锋. 一种面向忆阻器加速器的神经网络模型压缩框架[J]. 微电子学与计算机, 2021, 38(8): 20-27.

SHEN Linyao, WANG Qin, JIANG Jianfei, et al. Towards ReRAM-based Accelerator: An Energy-efficient NN Model Compression Framework[J]. 2021, 38(8): 20-27.
沈林耀, 王琴, 蒋剑飞, 景乃锋. 一种面向忆阻器加速器的神经网络模型压缩框架[J]. 微电子学与计算机, 2021, 38(8): 20-27. DOI：

SHEN Linyao, WANG Qin, JIANG Jianfei, et al. Towards ReRAM-based Accelerator: An Energy-efficient NN Model Compression Framework[J]. 2021, 38(8): 20-27. DOI：

摘要

当前基于忆阻器的神经网络加速器存在的资源需求高、系统功耗大等问题，提出了一种包含剪枝及量化算法在内的神经网络模型压缩框架.根据忆阻器阵列紧密耦合的特点，设计了一种忆阻器阵列感知的规则化增量剪枝算法，在保证模型准确度的条件下实现了硬件资源的节省；针对忆阻器加速器系统中ADC单元和忆阻器阵列功耗占比过大等问题，设计了一种二的幂次量化算法以降低加速器系统中ADC的精度需求以及计算阵列中低阻值忆阻器器件个数，实现系统功耗的降低.实验结果表明：提出的神经网络模型压缩框架在忆阻器加速器部署网络时可取得17.2~30.7倍的能效提升以及4.3~9.3倍的加速比，模型的精度损失维持在1%左右.

Abstract

The current ReRAM-based NN acceleratorshave many problems such as high hardwareresource demand and high power consumption. An energy-efficient modelcompression framework consisting of pruning and quantization algorithms is proposed. According to the tightly coupled crossbar structure and unstructured sparsity

a crossbar-aware incrementalstructured pruning algorithm is designedtoachievehigher sparsity and accuracy. A power of two quantizationmethod is designedto reduce ADC resolution requirements and the numberof low resistance states (LRS) ReRAM cells in crossbars to improvethe energy efficiency. Experimental results show thatthe proposed modelcompression framework can achieve 17.2-30.7x energy efficiencyand 4.3-9.3x speedup

compared with ReRAM-based acceleratorsfor dense NN with about 1% accuracy loss

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references

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HU M, STRACHAN J P, LI Z Y, et al. Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication[C]//2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). Austin, TX, USA: IEEE, 2016: 1-6. DOI: 10.1145/2897937.2898010.

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DONG X Y, XU C, XIE Y, et al. NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012, 31(7): 994-1007. DOI: 10.1109/TCAD.2012.2185930.

JI H X, SONG L H, JIANGL, et al. ReCom: An efficient resistive accelerator for compressed deep neural networks[C]//2018 Design, Automation % Test in Europe Conference % Exhibition (DATE). Dresden, Germany: IEEE, 2018: 237-240. DOI: 10.23919/DATE.2018.8342009.

WANG P Q, JI Y, HONGC, et al. SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory[C]//2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). San Francisco, CA, USA: IEEE, 2018: 1-6. DOI: 10.1109/DAC.2018.8465793.

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