Subtraction topology reconfigurable multiphase switched capacitor DC-DC converter with conductance modulation

KANG Haopeng; Wang Xiaofei; Jin Jing

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Subtraction topology reconfigurable multiphase switched capacitor DC-DC converter with conductance modulation

更新时间：2026-09-04

- Subtraction topology reconfigurable multiphase switched capacitor DC-DC converter with conductance modulation
- Vol. 38, Issue 7, Pages: 13-17(2021)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
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- Published：2021
- 稿件说明：
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康昊鹏, 王霄飞, 金晶. 电导调制的相减拓扑可重构多相开关电容DC-DC[J]. 微电子学与计算机, 2021, 38(7): 13-17.

KANG Haopeng, Wang Xiaofei, Jin Jing. Subtraction topology reconfigurable multiphase switched capacitor DC-DC converter with conductance modulation[J]. 2021, 38(7): 13-17.
康昊鹏, 王霄飞, 金晶. 电导调制的相减拓扑可重构多相开关电容DC-DC[J]. 微电子学与计算机, 2021, 38(7): 13-17. DOI：

KANG Haopeng, Wang Xiaofei, Jin Jing. Subtraction topology reconfigurable multiphase switched capacitor DC-DC converter with conductance modulation[J]. 2021, 38(7): 13-17. DOI：

摘要

提出了相减模式的可重构多相位开关电容DC-DC变换器，实现1/2和2/3两种转换比.在2/3模式下，利用减法拓扑降低了传统串并联架构中的寄生损耗.给出了多相位开关电容DC-DC在脉冲频率调制下的环路小信号模型；提供了开关频率和开关管尺寸在给定负载条件下的最佳选择方案.采用比较器实现了开关管尺寸的自适应调制，进一步提升了效率.仿真结果显示：基于40 nm工艺，该变换器的输入电压为2.2 V，环路带宽达到了20 MHZ，瞬态响应的恢复时间为40 ns；变换器在1/2模式下，达到了85.2%的峰值效率和280 mW/mm的功率密度；在2/3模式下，达到了83.7%的峰值效率和320 mW/mm的功率密度.

Abstract

A subtraction topology of the reconfigurable multiphase switched capacitor DC-DC converter is presented to realize the conversion ratios of 1/2 and 2/3. In 2/3 mode

the parasitic loss of the serial-parallel topology is reduced by the subtraction topology. This paper presents the small signal model of the multiphase switched capacitor DC-DC converter loop under PFM control

which provides the optimal selection scheme for the switching frequency and the size of the transistors at a given load condition. The comparator is adopted to realize the adaptive modulation of the conductance of the transistors to further improve the efficiency. The simulation results show that under 2.2 V input voltage in the TSMC-40nm process

the proposed converter achieves 20 MHz bandwidth. The recovery time of the transient response is 40ns. In 1/2 mode

this converter achieves the peak efficiency of 85.2% and the power density of 280 mW/mm2. In 2/3 mode

the peak efficiency is 83.7% and the power density is 320 mW/mm.

关键词

Keywords

references

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方贤朋, 孙业钦, 王兴华. 一种低功耗高效率DC-DC转换器的设计实现[J]. 微电子学与计算机, 2019, 36(12): 69-71. DOI:10.19304/j.cnki.issn1000-7180.2019.12.014. FANG X P, SUN Y Q, WANG X H. A low power high efficienecy DC-DC converter[J]. Microelectronics % Computer, 2019, 36(12): 69-71. DOI:10.19304/j.cnki.issn1000-7180.2019.12.014.

王晖, 张涛, 刘劲. 一种用于Buck型DC-DC电源管理芯片的带隙基准源[J]. 微电子学与计算机, 2020, 37(10): 42-47. DOI:10.19304/j.cnki.issn1000-7180.2020.10.008. WANG H, ZHANG T, LIU J. A bandgap reference source for buck DC-DC power management chip[J]. Microelectronics % Computer, 2020, 37(10): 42-47. DOI:10.19304/j.cnki.issn1000-7180.2020.10.008.

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