Using direct programming interface technology to improve the reusability of UVM verification of system on chip

REN Chuan-bao; CUI Jian-guo; LU Ying-chun; HUANG Zheng-feng; YI Mao-xiang

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Using direct programming interface technology to improve the reusability of UVM verification of system on chip

更新时间：2026-09-04

- Using direct programming interface technology to improve the reusability of UVM verification of system on chip
- Vol. 38, Issue 6, Pages: 20-26(2021)
- 作者机构：
  
  合肥工业大学电子科学与应用物理学院,合肥,230009
- 作者简介：
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- Published：2021
- 稿件说明：
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任传宝, 崔建国, 鲁迎春, 黄正峰, 易茂祥. 应用直接编程接口技术提高片上系统的UVM验证重用性[J]. 微电子学与计算机, 2021, 38(6): 20-26, 32.

REN Chuan-bao, CUI Jian-guo, LU Ying-chun, et al. Using direct programming interface technology to improve the reusability of UVM verification of system on chip[J]. 2021, 38(6): 20-26.
任传宝, 崔建国, 鲁迎春, 黄正峰, 易茂祥. 应用直接编程接口技术提高片上系统的UVM验证重用性[J]. 微电子学与计算机, 2021, 38(6): 20-26, 32. DOI：

REN Chuan-bao, CUI Jian-guo, LU Ying-chun, et al. Using direct programming interface technology to improve the reusability of UVM verification of system on chip[J]. 2021, 38(6): 20-26. DOI：

摘要

提出一种提高片上系统的UVM验证重用性方案，应用直接编程接口技术，实现通用验证方法学和C语言程序的交互通信.该方法不仅降低了通用验证方法学使用的复杂度，而且使得C语言测试用例可以在不同的测试层次中移植重用，例如C测试代码可以从模块级到片上系统级的重用.以SPI控制器验证本方案，搭建其UVM验证平台，编写大量的UVM和C测试用例，使其功能覆盖率达到100%，并通过虚拟处理器方案保证C测试用例从模块级复用到系统级的可行性.实验过程中激励开发简单且调试方便，可以实现UVM环境和测试用例的重用，从而提高片上系统的UVM验证重用性，达到缩短芯片开发时间的目的.

Abstract

This paper proposes a scheme to improve the reusability of UVM verification for system on chip. The direct programming interface (DPI) technology is applied to realize the interactive communication between universal verification methodology and C-language program

which not only reduces the complexity of using universal verification methodology

but also makes C-language test cases portable and reused in different test levels

for example

C-test code can be reused from module level to system on chip level. The SPI controller was used to verify the scheme

the UVM verification platform was built

a large number of UVM and C test cases were written to achieve 100% functional coverage

and the feasibility of C test cases being reused from module level to system level was guaranteedthrough the virtual processor scheme. During the experiment

the incentive development is simple and debugging is convenient. It can realize the reuse of UVM environment and test cases

to improve the reusability of UVM verification of system on chip and shorten the development time of chip.

关键词

Keywords

references

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