Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips

RUAN Hua-jie; GE Meng-ke; CHEN Song

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Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips

更新时间：2026-09-04

- Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips
- Vol. 38, Issue 1, Pages: 12-16(2021)
- 作者机构：
  
  中国科学技术大学,安徽,合肥,230026
- 作者简介：
- 基金信息：
- DOI：
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- Published：2021
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阮华杰, 葛梦柯, 陈松. 基于拉格朗日松弛的多容错专用片上网络拓扑生成[J]. 微电子学与计算机, 2021, 38(1): 12-16, 21.

RUAN Hua-jie, GE Meng-ke, CHEN Song. Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips[J]. 2021, 38(1): 12-16.
阮华杰, 葛梦柯, 陈松. 基于拉格朗日松弛的多容错专用片上网络拓扑生成[J]. 微电子学与计算机, 2021, 38(1): 12-16, 21. DOI：

RUAN Hua-jie, GE Meng-ke, CHEN Song. Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips[J]. 2021, 38(1): 12-16. DOI：

摘要

随着半导体技术的进步

专用片上网络(ASNoC)成为解决纳米级片上系统通信问题的有效方案.本文提出了一种基于拉格朗日松弛的ASNoC容错拓扑生成方法

可实现大规模ASNoC用户自定义K容错拓扑生成.该ASNoC的容错拓扑生成方法不仅考虑片上网络中可能发生的链路或路由器故障

而且对于用户定义的容错数量K

可以容忍路由器或链路中存在至少K个错误.该方法同时求解IP核映射问题和路由路径分配问题

在满足约束条件下最大程度地降低功耗.实验结果表明

提出的方法显著降低了功耗、物理链路、跳数和运行时间.同时它在可接受的运行时间下实现了大规模ASNoC的容错拓扑生成.

Abstract

With the development of semiconductor technology

application specific network-on-chip (ASNoC) has become an effective solution to the communication problems of nanoscale system-on-chips. This paper presents an ASNoC fault-tolerant topology generation method based on Lagrangian relaxation

which can realize large-scale user-defined K-fault-tolerant topology generation of ASNoC. The fault-tolerant topology generation method of ASNoC not only considers the possible link or router failures in the on-chip network

but also tolerates at least K errors in the router or link for the user-defined fault-tolerant number K. The IP core mapping problem and routing path allocation problem are solved simultaneously

and the power consumption is reduced to the maximum extent under the constraint conditions. The experimental results show that the proposed method significantly reduces power consumption

physical links

hops and running time. Meanwhile

it achieves a large-scale ASNoC fault-tolerant topology with acceptable runtime.

关键词

Keywords

references

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CHEN S, GE M K, LI Z G, et al. Generalized fault-tolerance topology generation for application-specific network-on-chips[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(6): 1191-1204. DOI: 10.1109/TCAD.2019.2952134.

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ZHONG W, YU B, CHEN S, et al. Application-specific network-on-chip synthesis: cluster generation and network component insertion[C]//Proceedings of 2011 12th International Symposium on Quality Electronic Design.Santa Clara, CA, USA: IEEE, 2011: 1-6. DOI: 10.1109/ISQED.2011.5770718.

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