An acceleration scheme for reconfigurable multi-core system

NIU Yun-peng; ZHANG Duo-li; TANG Xu; SONG Yu-kun

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An acceleration scheme for reconfigurable multi-core system

更新时间：2026-09-04

- An acceleration scheme for reconfigurable multi-core system
- Vol. 38, Issue 2, Pages: 19-24(2021)
- 作者机构：
  
  1. 合肥工业大学微电子设计研究所,安徽,合肥,230601
  2. 教育部IC设计网上合作研究中心,安徽,合肥,230601
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2021
- 稿件说明：
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牛云鹏, 张多利, 唐旭, 宋宇鲲. 一种可重构多核系统的仿真加速方案[J]. 微电子学与计算机, 2021, 38(2): 19-24.

NIU Yun-peng, ZHANG Duo-li, TANG Xu, et al. An acceleration scheme for reconfigurable multi-core system[J]. 2021, 38(2): 19-24.
牛云鹏, 张多利, 唐旭, 宋宇鲲. 一种可重构多核系统的仿真加速方案[J]. 微电子学与计算机, 2021, 38(2): 19-24. DOI：

NIU Yun-peng, ZHANG Duo-li, TANG Xu, et al. An acceleration scheme for reconfigurable multi-core system[J]. 2021, 38(2): 19-24. DOI：

摘要

针对可重构多核系统多任务仿真耗时长、并发性差的问题，提供了一种分层的、以资源请求异步响应为特点的松耦合多精度多线程系统建模方案.采用此方案的系统模型在任务仿真时，不仅能够提供寄存器级的实时数据反馈，同时也具有优异的任务并发性能.实验显示，相对于传统上位机软件数据收集和计算，该模拟器周期预测相对误差小于3%，模拟计算相对误差小于2e-5，仿真耗时最大缩短73.52%；在启用任务异步响应优化后，任务并行度平均提升28.21%.该设计在硬件目标系统的快速性能评估方面具有良好的实用价值.

Abstract

This paper provides a layered

loosely coupled

multi-precision

multi-threaded system modeling for solving the problem of time-consuming of multi-task simulation and poor concurrency in reconfigurable multi-core system. The system model using this scheme can not only provide register-level real-time data feedback during task simulation

but also have excellent task concurrency performance. Experiments show that

compared with the data collection and calculation of traditional host computer software

the relative error of the simulator′s period prediction is less than 3%

the relative error of simulation calculation is less than 2e-5

and the simulation time is shortened by a maximum of 73.52%; after enabling the task asynchronous response optimization

Task parallelism increased by an average of 28.21%. The design has good practical value in the rapid performance evaluation of the hardware target system.

关键词

Keywords

references

NOLTING S, PAYÁ-VAYÁ G, GIESEMANN F, et al. Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture[J]. Journal of Parallel and Distributed Computing, 2019, 133: 391-406. DOI: 10.1016/j.jpdc.2017.09.013.

WEI Y. Construct multi-coreDSP software simulation platform based on SystemC[J]. Microelectronics% Computer, 2016, 33(4): 86-90. DOI: 10.19304/j.cnki.issn1000-7180.2016.04.019.

HE W Q, YANG L, LU Q. Cycle-accurate DSP processor modelingwithSystemC[J]. Microelectronics % Computer, 2013, 30(4): 107-110. DOI: 10.19304/j.cnki.issn1000-7180.2013.04.026.

KIRCHSTEIGER C M, SCHWEITZER H, TRUMMER C, et al. A software performance simulation methodology for rapid system architecture exploration[C]//Proceedings ofthe 15th IEEE International Conference on Electronics, Circuits and Systems. St. Julien's, Malta: IEEE, 2008: 494-497. DOI: 10.1109/ICECS.2008.4674898.

CHEN H, LUO W L, GAN Y Y. Multi_MINT: A multiprocessor simulator basedonMINT[J]. ComputerEngineering% Science, 2011, 33(12): 37-43. DOI: 10.3969/j.issn.1007-130X.2011.12.007.

YU J, LI X, ZHOU X H, et al. Study on retargetable cycle-accurate simulator generation environment[J]. Journal of Chinese Computer Systems, 2007, 28(1): 166-171. DOI: 10.3969/j.issn.1000-1220.2007.01.036.

EGGER B, SONG E, LEE H, et al. Random test program generation for verification and validation of the Samsung Reconfigurable Processor[J]. Journal of Systems Architecture, 2019, 97: 219-238. DOI: 10.1016/j.sysarc.2019.05.007.

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