Research on verification method of processor based on genetic evolution strategy

YANG Kai-feng; ZHANG Xue-qian; FENG Jiao; LIANG Feng

Chinese

您当前的位置：

首页 >

文章列表页 >

Research on verification method of processor based on genetic evolution strategy

更新时间：2026-09-04

- Research on verification method of processor based on genetic evolution strategy
- Vol. 38, Issue 5, Pages: 25-29(2021)
- 作者机构：
  
  西安交通大学微电子学院,陕西,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2021
- 稿件说明：
移动端阅览
杨凯峰, 张雪倩, 冯娇, 梁峰. 基于遗传进化策略的处理器验证方案[J]. 微电子学与计算机, 2021, 38(5): 25-29.

YANG Kai-feng, ZHANG Xue-qian, FENG Jiao, et al. Research on verification method of processor based on genetic evolution strategy[J]. 2021, 38(5): 25-29.
杨凯峰, 张雪倩, 冯娇, 梁峰. 基于遗传进化策略的处理器验证方案[J]. 微电子学与计算机, 2021, 38(5): 25-29. DOI：

YANG Kai-feng, ZHANG Xue-qian, FENG Jiao, et al. Research on verification method of processor based on genetic evolution strategy[J]. 2021, 38(5): 25-29. DOI：

摘要

RISC-V作为近年来发展迅速的开源处理器架构，对其验证方法的研究具有很高的工业应用价值.提出了基于遗传进化策略的处理器验证优化方案，利用遗传算法产生指令的权重系数，为测试用例的生成确定方向，并对RISC-V处理器RV32I部分指令完成了模拟验证.与基于伪随机策略生成测试用例的方案相比，应用遗传进化策略生成测试用例时，能够维持对功能覆盖率贡献更高的方向，在验证末期即将陷入局部最优解时，仍然能够突破当前状态，使整体功能覆盖率进一步提高.同时，该验证优化方案对验证环境的调整实现了完全自动化，具有较高的可扩展性和可维护性.

Abstract

As an open source processor architecture with rapid development in recent years

RISC-V has high industrial application value in the research of its verification method. In this paper

an optimization scheme of processor verification based on the genetic evolution strategy is proposed

which uses a genetic algorithm to generate instruction weight coefficients to determine the direction for the generation of test cases

and some instructions of RV32I of the RISC-V processor are simulated and verified.Compared with the scheme based on the pseudo-random strategy to generate test cases

the application of genetic evolution strategy to generate test cases can maintain a higher contribution to the function coverage.When it is about to fall into a locally optimal solution at the end of verification

it is still able to break out of the current state

allowing a further improvement of the overall functional coverage. At the same time

the verification optimization scheme realizes the automatic adjustment of the verification environment and has high scalability and maintainability.

关键词

Keywords

references

王璇. 基于UVM的FPGA中可编程逻辑块的验证[D]. 西安: 西安电子科技大学, 2019. WANG X. The UVM-based verification of the CLB in FPGA[D]. Xi'an: Xidian University, 2019.

Beijing 刘斌. 芯片验证漫游指南[M]. 北京: 电子工业出版社, 2018. LIU B. Walking guide to SOC verification[M]. Beijing: Publishing House of Electronics Industry, 2018.

FAJCIK M, SMRZ P, ZACHARIASOVA M. Automation of processor verification using recurrent neural networks[C]//2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV). Austin: IEEE, 2017: 15-20. DOI: 10.1109/MTV.2017.15.

GHOSH P. Analysis and verification of SoC design RTL parameters[C]//2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). Delhi: IEEE, 2016: 1-6. DOI: 10.1109/ICPEICES.2016.7853486.

Boston SANCHEZ E, SCHILLACIM, SQUILLERO G. Evolutionary optimization: the Micro GP toolkit[M]. Boston: Springer Science and Business Media, 2011. DOI: 10.1007/978-0-387-09426-7.

Heidelberg EIBEN A E, SMITH J E. Introduction to evolutionary computing[M]. Heidelberg: Springer-Verlag Berlin Heidelberg, 2003. DOI: 10.1007/978-3-662-05094-1.

傅亮, 卢鼎, 张志敏, 等. 通过分析代码覆盖提高功能覆盖率的验证输入自动生成方法[J]. 计算机辅助设计与图形学学报, 2009, 21(4): 454-460. DOI: 454 FU L, LU D, ZHANG Z M, et al. An automatic test generation method for functional coverage improvement by code coverage analysis[J]. Journal of Computer-Aided Design % Computer Graphics, 2009, 21(4): 454-460. DOI: 454

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

A RISC-V vector processor computation method based on instruction serial fusion

System level single event upset hardening design based on RISC-V architecture

Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor

Design of an adaptive reconfigurable general-purpose floating-point accelerator

Design of RISC-V processor based on Chisel

Related Author

YANG Mengfei

GAO Xin

LI Kaige

SU Ruohao

HUANG Jiuyu

ZHAO Cuihua

LUO Mintao

XU Jihang

Related Institution

Beijing Institute of Control Engineering, China Academy of Space Technology

Beijing SunWise Information Technology Ltd

Xi'an Microelectronics Technology Institute

Engineering Research Center of Internet of Things Technology Applications, Ministry of Education

Department of Electronic Engineering, Jiangnan University

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰