Design and implementation of FPGA-based real time multiple face detection system

LI Bin; XU Hua-jie; WU Zhao-hui

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Design and implementation of FPGA-based real time multiple face detection system

更新时间：2026-09-04

- Design and implementation of FPGA-based real time multiple face detection system
- Vol. 38, Issue 4, Pages: 57-62(2021)
- 作者机构：
  
  1. 华南理工大学微电子学院,广东,广州,510641
  2. 人工智能与数字经济广东省实验室(广州),广东,广州,510641
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2021
- 稿件说明：
移动端阅览
李斌, 许华杰, 吴朝晖. 基于FPGA的多人脸实时检测系统设计与实现[J]. 微电子学与计算机, 2021, 38(4): 57-62.

LI Bin, XU Hua-jie, WU Zhao-hui. Design and implementation of FPGA-based real time multiple face detection system[J]. 2021, 38(4): 57-62.
李斌, 许华杰, 吴朝晖. 基于FPGA的多人脸实时检测系统设计与实现[J]. 微电子学与计算机, 2021, 38(4): 57-62. DOI：

LI Bin, XU Hua-jie, WU Zhao-hui. Design and implementation of FPGA-based real time multiple face detection system[J]. 2021, 38(4): 57-62. DOI：

摘要

设计了一种基于移动端深度学习目标检测算法MobileNetV2- SSDlite的小规模、高精度的人脸检测算法.在算法基础上，围绕硬件架构、片上缓存、性能及功耗等方面进行移动端专用型神经网络加速器的研究与设计; 在ALINX AX7350 SOC平台上实现了实时多人脸检测加速器系统.结果表明，本系统在100 MHz时钟下，平均计算性能为56.01 GOPS，功耗为7.3 W.与现有的MobileNetV2-SSDlite加速器相比，运算速度提高了28.7%，资源平均节省了44.46%，功耗降低了26.3%.在224×224分辨率下，达到了83.4 FPS，满足实时性需求.

Abstract

A small and high-precision face detection algorithm based on MobileNetV2-SSDlite is designed. To improve the computing capability of mobile terminals

the study of the mobile algorithm specific neural network accelerator is carried out in terms of hardware architecture

on-chip memory

performance and power consumption. A real-time multi-face detection accelerator system is simulated and implemented on ALINX AX7350 SOC platform. The results show that under a 100MHz clock

the face detection system has an average computing performance of 56.01 GOPS and a power consumption of 7.3W. Compared with the existing MobileNetV2-SSDlite accelerator

the operation speed is improved by 28.7%

the resources are reduced by 44.46%

and the power consumption is reduced by 26.3%. The speed of the system in inferencing a 224×224 resolution picture reached 83.4 FPS

meet the demand of real-time performance.

关键词

Keywords

references

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LIU B, ZOU D Y, FENG L, et al. An FPGA-based CNN accelerator integrating depthwise separable convolution[J]. Electronics, 2019, 8(3): 281. DOI: 10.3390/electronics8030 281.

XU H J, WU Z H, DING J, et al. FPGA based real-time multi-face detection system with convolution neural network[C]//Proceedings of the 2019 8th International Symposium on Next Generation Electronics. Zhengzhou: IEEE, 2019: 1-3. DOI: 10.1109/ISNE.2019.8896551.

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FAN H X, LIU S L, FERIANC M, et al. A real-time object detection accelerator with compressed SSDLite on FPGA[C]//Proceedings of 2018 International Conference on Field-Programmable Technology. Naha: IEEE, 2018: 14-21. DOI: 10.1109/FPT.2018.00014.

ZHANG K P, ZHANG Z P, LI Z F, et al. Joint face detection and alignment using multitask cascaded convolutional networks[J]. IEEE Signal Processing Letters, 2016, 23(10): 1499-1503. DOI: 10.1109/LSP.2016.2603342.

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