
- Home
高级 检索
Chinese
English



1. 合肥工业大学 电子科学与应用物理学院,合肥,230009
2. 合肥工业大学 数学学院,安徽,合肥,23009
Published:2020
移动端阅览
左小寒, 梁华国, 杨兆, 束月, 蒋翠云. 基于菱形分组器的TSV聚簇故障容错结构[J]. 微电子学与计算机, 2020, 37(11): 48-53.
ZUO Xiao-han, LIANG Hua-guo, YANG Zhao, et al. A new TSV fault-tolerant architecture for clustered faults based on diamond burster[J]. 2020, 37(11): 48-53.
基于硅通孔的三维集成电路具备低互连延时、高密度、低功耗等优势.然而
由于不成熟的工艺技术
TSV制造堆叠及芯片绑定过程容易引入微孔、泄漏等缺陷
造成TSV故障.并且
这些TSV故障易呈现聚簇分布
严重降低三维集成电路的良率.针对TSV聚簇故障
本文提出了一种新的基于菱形分组器的TSV聚簇故障容错结构.以菱形分组器将TSV蜂窝阵列划分为若干TSV组
为每组配置相应的修复资源
达到分散TSV聚簇故障后逐个修复的目的
并以数据选择器链共享修复资源.实验结果表明
本文结构针对聚簇或均匀分布的TSV故障修复率均达到了99%
远高于同类方法
良好适用于修复TSV聚簇及均匀故障.
The three-dimensional integrated circuit based on though-silicon-vias has the advantages of low interconnect delay
high density and low power consumption. However
due to the immature technology
the manufacturing
stacking of TSVs and the binding of chips are prone to introduce micro-hole
leakage and other defects
causing TSV faults. Moreover
these TSV faults tend to distribute clustered
which seriously reduces the yield of three-dimensional integrated circuit. A new TSV fault-tolerant architecture for clustered faults based on diamond burster is proposed in this paper. The TSV honeycomb block is divided into several TSV groups by diamond burster
and corresponding repair resources are configured for each group
so as to disperse the clustered TSV faults and repair them one by one. Multiplexer-chains are used to share the repair resources. Experimental results show that the repair rates of the proposed architecture for clustered or uniformly distributed TSV faults maintain above 99%
far higher than similar method
which indicates that the proposed architecture is well applicable to repairing clustered and uniformly distributed TSV faults.
NI T M, YAO Y, CHANG H, et al. LCHR-TSV: novel low cost and highly repairable honeycomb-based TSV redundancy architecture for clustered faults[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, DOI: 10.1109/TCAD.2019.2946243.
WALDROP M M. The chips are down for Moore′s law[J]. Nature, 2016, 530(7589): 144-147. DOI:10.1038/530 144a.
CHEN S, XU Q, YU B. Adaptive 3D-IC TSV Fault Tolerance structure generation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38(5): 949-960. DOI:10.1109/TCAD.2018.2824284.
LO W H, CHI K, HWANG T T. Architecture of ring-based redundant TSV for clustered faults[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2016, 24(12): 3437-3449. DOI:10.1109/TVLSI.2016.2558514.
JIANG L, XU Q, EKLOW B. On Effective Through-Silicon Via Repair for 3-D-Stacked ICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(4): 559-571. DOI:10.1109/TCAD.2012.2228742.
LEE C Y, KIM S, JUN H, et al. TSV technology and challenges for 3D stacked DRAM[C]//Proceedings of 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers. Honolulu: IEEE, 2014: 1-2. DOI: 10.1109/VLSIT.2014.6894397.
HSIEH A C, HWANG T T. TSV redundancy: architecture and design issues in 3-D IC[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(4): 711-722. DOI:10.1109/TVLSI.2011.2107924.
HOSSAIN N M, KUCHUKULLA R K R, CHOWDHURY M H. Failure analysis of the through silicon via in three-dimensional integrated circuit (3D-IC)[C]//Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS). Florence: IEEE, 2018: 1-4. DOI: 10.1109/ISCAS.2018.8351020.
AGARWAL R, ZHANG W Q, LIMAYE P, et al. Cu/Snmicrobumpsinterconnect for 3D TSV chip stacking[C]//Proceedings of the 60th Electronic Components and Technology Conference (ECTC).Las Vegas: IEEE, 2010: 858-863. DOI: 10.1109/ECTC.2010.5490698.
KANG U, CHUNG H J, HEO S, et al. 8Gb 3D DDR3 DRAM using through-silicon-via technology[C]//Proceedings of 2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers. San Francisco, IEEE, 2009: 130-131. DOI: 10.1109/ISSCC.2009.4977342.
EGHBAL A, YAGHINI P M, BAGHERZADEH N, et al. Analytical fault tolerance assessment and metrics for TSV-Based 3D network-on-chip[J]. IEEE Transactions on Computers, 2015, 64(12): 3591-3604. DOI:10.1109/TC.2015.2401016.
KITADA H, SUZUKI T, KIMURA T, et al. The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology[C]//Proceedings of 2007 IEEE International Interconnect Technology Conference.Burlingame, IEEE, 2007: 10-12. DOI: 10.1109/IITC.2007.382333.
FRANK T, MOREAU S, CHAPPAZ C, et al. Reliability of TSV interconnects: electromigration, thermal cycling, and impact on above metal level dielectric[J]. Microelectronics Reliability, 2013, 53(1): 17-29. DOI:10.1016/j.microrel.2012.06.021.
GOLDBERG A V, RAO S. Beyond the flow decomposition barrier[J]. Journal of the ACM, 1998, 45(5): 783-797. DOI:10.1145/290179.290181.
LOI I, MITRA S, LEE T H, et al. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links[C]//Proceedings of 2008 IEEE/ACM International Conference on Computer-aided Design. San Jose, IEEE, 2008: 598-602. DOI: 10.1109/ICCAD.2008.4681638.
0
Views
12
下载量
0
CSCD
Publicity Resources
Related Articles
Related Author
Related Institution
京公网安备11010602201714号