A 10 bit 40 KS/s low-power SAR ADC for bio-electrical signal acquisition

LUO Jing; ZHAO Jian; CHEN Ming-yi; WANG Guo-xing

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A 10 bit 40 KS/s low-power SAR ADC for bio-electrical signal acquisition

更新时间：2026-09-04

- A 10 bit 40 KS/s low-power SAR ADC for bio-electrical signal acquisition
- Vol. 37, Issue 12, Pages: 64-69(2020)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
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罗京, 赵健, 陈铭易, 王国兴. 适用于生物电信号采集的低功耗10 bit 40 KS/s SAR ADC设计[J]. 微电子学与计算机, 2020, 37(12): 64-69.

LUO Jing, ZHAO Jian, CHEN Ming-yi, et al. A 10 bit 40 KS/s low-power SAR ADC for bio-electrical signal acquisition[J]. 2020, 37(12): 64-69.
罗京, 赵健, 陈铭易, 王国兴. 适用于生物电信号采集的低功耗10 bit 40 KS/s SAR ADC设计[J]. 微电子学与计算机, 2020, 37(12): 64-69. DOI：

LUO Jing, ZHAO Jian, CHEN Ming-yi, et al. A 10 bit 40 KS/s low-power SAR ADC for bio-electrical signal acquisition[J]. 2020, 37(12): 64-69. DOI：

摘要

设计了一款适用于生物电信号采集的低功耗10 bit分辨率、40 KS/s采样率的逐次逼近型模数转换器(SAR ADC).为了降低电容阵列的切换功耗

提出了一种新型混合型电容切换方式.该混合型电容切换方式将共模电平单调向下切换与基于共模电平的切换方式相结合

有效地实现了电容阵列的低功耗切换.与传统共模电平不变的电容切换方式相比

采用了混合型电容切换方式能够使电容切换耗能降低90.7%.与共模电平单调向下切换和基于共模电平切换相比

该混合型电容切换方式也能够使电容切换耗能分别降低50.2%和25.3%.该款ADC采用TSMC 0.18m CMOS工艺进行设计

后仿真结果表明

在40 KS/s采样速率

输入为满量程接近奈奎斯特频率的正弦信号下

该款ADC可以得到9.6 bit有效位数(ENOB)

无杂散动态范围(SFDR)为73.2 dB

总功耗为2.1 W

品质因数(FoM)为68 fJ/(Conv-step).

Abstract

A 10 bit

40 KS/s low-power successive approximation register analog-to-digital converter (SAR ADC) is designed for bio-electrical signal acquisition. To reduce the switching power of capacitors

a new hybrid switching scheme is proposed. Based on the monotonic switching method and the V-based switching method

this proposed switching scheme can achieve low-power switching of capacitors effectively. Compared with the conventional V-constant switching scheme

the hybrid switching method can reduce the switching energy by 90.7%. Compared with the monotonic switching method and the V-based switching method

this new proposed method can reduce the switching energy by 50.2% and 25.3%

respectively.Implemented in TSMC 0.18m CMOS process

the post-simulation results show that the hybrid ADC achieves the effective number of bits (ENOB) of 9.6 bit

the spurious free dynamic range (SFDR) of 73.2 dB and the Figure of Merit (FoM)of 68 fJ/(Conv-step) at 40 KS/s sampling rate with full-scalenear Nyquist input

with power consumption of 2.1 W.

关键词

Keywords

references

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