Research on theoptimized design of anti-SEU for bus controller chip

JIANG Shuang; LIU Shi-bin; GUO Chen-guang; PENG Bin; FAN Xu

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Research on theoptimized design of anti-SEU for bus controller chip

更新时间：2026-09-04

- Research on theoptimized design of anti-SEU for bus controller chip
- Vol. 37, Issue 12, Pages: 81-86(2020)
- 作者机构：
  
  1. 西北工业大学电子信息学院,陕西,西安,710129
  2. 北京微电子技术研究所机构,北京,100074
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
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姜爽, 刘诗斌, 郭晨光, 彭斌, 樊旭. 通用总线控制器抗SEU加固设计研究[J]. 微电子学与计算机, 2020, 37(12): 81-86.

JIANG Shuang, LIU Shi-bin, GUO Chen-guang, et al. Research on theoptimized design of anti-SEU for bus controller chip[J]. 2020, 37(12): 81-86.
姜爽, 刘诗斌, 郭晨光, 彭斌, 樊旭. 通用总线控制器抗SEU加固设计研究[J]. 微电子学与计算机, 2020, 37(12): 81-86. DOI：

JIANG Shuang, LIU Shi-bin, GUO Chen-guang, et al. Research on theoptimized design of anti-SEU for bus controller chip[J]. 2020, 37(12): 81-86. DOI：

摘要

随着集成电路制造技术的发展

寄存器和SRAM等存储单元在空间辐射环境中越来越容易受到单粒子翻转(SEU)效应的影响.传统抗SEU加固方法分为工艺加固和设计加固

前者依赖于工艺平台

难度大、周期长

后者仅针对芯片内部特定SEU敏感单元.通过提出一种针对通用总线控制器的芯片级抗SEU加固设计方法

采用冗余编码和刷新技术

可以进一步提高芯片的抗SEU能力; 通过划分影响域和添加中断源

便于定位芯片中SEU敏感位置

从而有利于片内刷新操作和后续设计优化.实验结果表明

与传统的辐射加固方法相比

新方法具有更高的辐射可靠性和容错能力.

Abstract

With the development of integrated circuit manufacturing technology

memory cells such as registers and SRAMs are more and more vulnerable to single-event upset (SEU) effect in space radiation environment. There are two traditional anti-SEU methods

i.e. manufacturing process reinforcement and design reinforcement. The former depends on the process platform

which is difficult and has a long period. The latter is only for specific SEU sensitive elements of the chip. By proposing a chip-level anti-SEU reinforcement design method for an universal bus controller chip

using redundant coding and scrubbing methods

the anti-SEU ability of the chip can be further improved. Meanwhile

by dividing influence domain and adding interrupt sources

the chips SEU-sensitive elements can be easily identified

which is very convenient for in-system refreshing and subsequent optimization. Verified by SEU experiment

the proposed chip has higher radiation reliability and fault-tolerance than the chip with traditional radiation-hardening methods.

关键词

Keywords

references

MCMORROW D, LOTSHAW W T, MELINGER J S, et al. Single-event upset in flip-chip sram induced by through-wafer, two-photon absorption[J]. IEEE Transactions on Nuclear Science, 2005, 52(6): 2421-2425. DOI: 2421

AHMAD S, ZAHRA M, FAROOQ S Z, et al. Comparison of edac schemes for ddr memory in space applications[C] //2013 International Conference on Aerospace Science Engineering (ICASE). 2013: 1-5.

ZHANG L, XU J, FAN S, et al. Single event upset sensitivity of d-flip flop: Comparison of pdsoi with bulk si at 130 nm technology node[J]. IEEE Transactions on Nuclear Science, 2017, 64(1): 683-688. DOI: 683

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SUSHMA K, NAIDU C D, SAI Y P, et al. Design and implementation of high performance mil-std-1553b bus controller[C] //2017 IEEE 7th International Advance Computing Conference (IACC). 2017: 266-269.

JIANG S, LIU S, GUO C, et al. Implementation of arinc 659 bus controller for space-borne computers[J]. Electronics, 2019, 8: 435. DOI: 435

GUO C, XU J, JIANG S, et al. A Novel Universal Radiation-hardened FFT Chip Design[C] //2018 International Conference on Radiation Effects of Electronic Devices (ICREED). 2018: 1-4.

NAKAJIMA M, OIKAWA S. Analyzing behavior of less interrupt overhead architecture for effective cache utilization[C] //2014 Second International Symposium on Computing and Networking. 2014: 611-613.

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