Design of a new floating point multiplier based on hybrid compression structure

YAO Shangshang; SHEN Li

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Design of a new floating point multiplier based on hybrid compression structure

更新时间：2026-09-04

- Design of a new floating point multiplier based on hybrid compression structure
- Vol. 38, Issue 9, Pages: 74-78(2021)
- 作者机构：
  
  国防科技大学电子科学与技术系,湖南,长沙,410073
- 作者简介：
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- Published：2021
- 稿件说明：
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姚上上, 沈立. 基于混合压缩结构的新型浮点乘法器设计[J]. 微电子学与计算机, 2021, 38(9): 74-78.

YAO Shangshang, SHEN Li. Design of a new floating point multiplier based on hybrid compression structure[J]. 2021, 38(9): 74-78.
姚上上, 沈立. 基于混合压缩结构的新型浮点乘法器设计[J]. 微电子学与计算机, 2021, 38(9): 74-78. DOI：

YAO Shangshang, SHEN Li. Design of a new floating point multiplier based on hybrid compression structure[J]. 2021, 38(9): 74-78. DOI：

摘要

为了进一步提高浮点乘法器的性能，缩短浮点乘法器关键路径延时，提出了一种基于新型4-2压缩器和5-2压缩器的混合压缩结构.在Xillinx的xc7a35tcsg324开发板上，基于该结构实现了IEEE754标准的32位浮点乘法器.相较于现有的压缩方式，提出的新型压缩结构相较于现有的压缩方式，所使用的LUT资源减少了45，关键路径延时减少了0.004 ns.与传统浮点乘法器相比，关键路径延时由6.022 ns缩短至4.673 ns，提升了浮点乘法器的运算性能.

Abstract

In order to further improve the performance of Floating-Point Multiplier and shorten the critical path delay of Floating-Point Multiplier

a hybrid compression structure based on new 4-2 compressor and 5-2 compressor is proposed. On the xc7a35tcsg324 development board of xillinx

the 32-bit Floating-Point Multiplier of IEEE754 standard is implemented based on this structure. Compared with the existing compression methods

the LUT resource and critical path delay are reduced by 45 and 0.004ns respectively. Compared with the traditional Floating-Point Multiplier

the critical path delay is reduced from 6.022ns to 4.673ns

which improves the performance of the Floating-Point Multiplier.

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references

夏炜, 肖鹏. 一种高效双精度浮点乘法器[J]. 计算机测量与控制, 2013, 21(4): 1017-1020. DOI: 10.3969/j.issn.1671-4598.2013.04.060. XIA W, XIAO P. An efficient double-precision floating-point multiplier[J]. Computer Measurement % Control, 2013, 21(4): 1017-1020. DOI: 10.3969/j.issn.1671-4598.2013.04.060.

刘容, 赵洪深, 李晓今. 基于改进型选择进位加法器的32位浮点乘法器设计[J]. 现代电子技术, 2013, 36(16): 133-136. DOI: 10.3969/j.issn.1004-373X.2013.16.040. LIU R, ZHAO H S, LI X J. Design of 32-bit floating-point multiplier based on improved carry-select adder[J]. Modern Electronics Technique, 2013, 36(16): 133-136. DOI: 10.3969/j.issn.1004-373X.2013.16.040.

吴美琪, 赵宏亮, 刘兴辉, 等. 一种基于改进基4 Booth算法和Wallace树结构的乘法器设计[J]. 电子设计工程, 2019, 27(16): 145-150. DOI: 10.3969/j.issn.1674-6236.2019.16.032. WU M Q, ZHAO H L, LIU X H, et al. A design of multiplier based on modified Booth-4 algorithm and Wallace tree[J]. Electronic Design Engineering, 2019, 27(16): 145-150. DOI: 10.3969/j.issn.1674-6236.2019.16.032.

石敏, 王耿, 易清明. 基于改进的Booth编码和Wallace树的乘法器优化设计[J]. 计算机应用与软件, 2016, 33(5): 13-16. DOI: 10.3969/j.issn.1000-386x.2016.05.004. SHI M, WANG G, YI Q M. An optimised design of multiplier based on improved booth encoding and Wallace tree[J]. Computer Applications and Software, 2016, 33(5): 13-16. DOI: 10.3969/j.issn.1000-386x.2016.05.004.

IEEE. IEEEStd754TM-2008. IEEE standard for floating-point arithmetic[S]. New York: IEEE, 2008.

朱鑫标, 施隆照. 一种高压缩Wallace树的快速乘法器设计[J]. 微电子学与计算机, 2013, 30(2): 46-49. DOI: 10.19304/j.cnki.issn1000-7180.2013.02.012. ZHU XB, SHI LZ. A design of multiplier with high-compress Wallace tree[J]. Microelectronics % Computer, 2013, 30(2): 46-49. DOI: 10.19304/j.cnki.issn1000-7180.2013.02.012.

王佳乐, 胡越黎. 基于新型booth选择器和压缩器的乘法器设计[J]. 微电子学与计算机, 2020, 37(3): 5-8. DOI: 10.19304/j.cnki.issn1000-7180.2020.03.002. WANG J L, HU Y L. Design and implementation multiplier based on new booth selector and compressor[J]. Microelectronics % Computer, 2020, 37(3): 5-8. DOI: 10.19304/j.cnki.issn1000-7180.2020.03.002.

仲亚, 叶瑶瑶. 基于新型压缩器的乘法器设计[J]. 微电子学与计算机, 2019, 36(3): 28-31, 37. DOI: 10.19304/j.cnki.issn1000-7180.2019.03.006. ZHONG Y, YE Y Y. Design of multiplier based on new compressor[J]. Microelectronics % Computer, 2019, 36(3): 28-31. DOI: 10.19304/j.cnki.issn1000-7180.2019.03.006.

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