Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC

ZHAO Haonan; GUO Xuan; ZHOU Lei; WU Danyu; WU Jin

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Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC

更新时间：2026-09-04

- Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC
- Vol. 38, Issue 9, Pages: 93-98(2021)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构
- 作者简介：
- 基金信息：
- DOI：
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- Published：2021
- 稿件说明：
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赵浩男, 郭轩, 周磊, 吴旦昱, 武锦. 无采保流水线型ADC中比较器失调后台校准方法与FPGA实现[J]. 微电子学与计算机, 2021, 38(9): 93-98.

ZHAO Haonan, GUO Xuan, ZHOU Lei, et al. Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC[J]. 2021, 38(9): 93-98.
赵浩男, 郭轩, 周磊, 吴旦昱, 武锦. 无采保流水线型ADC中比较器失调后台校准方法与FPGA实现[J]. 微电子学与计算机, 2021, 38(9): 93-98. DOI：

ZHAO Haonan, GUO Xuan, ZHOU Lei, et al. Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC[J]. 2021, 38(9): 93-98. DOI：

摘要

为了解决超高速无采保流水线型ADC中比较器失调(包含孔径误差与静态比较器失调)对整体性能的影响问题，本文提出了一种后台数字校准方法.该方法通过在数字域对输出余差进行统计完成误差的检测，并在模拟域调节校准DAC完成误差的校准.校准基于余差均值之差和极值之和，分别对孔径误差和静态比较器失调进行迭代提取，避免了来自其他非理想因素的影响，提高了高频信号下ADC整体性能，有效提高了校准的稳定性.该方法应用于一款2.5 GS/s 12 bit ADC中，并基于FPGA进行实现.根据实际测试结果在输入信号频率为1.913 GHz时，校准后SNDR提高了8 dB.该校准方法降低了无采保流水线型ADC的设计难度和模拟电路的设计压力，为更高速、低功耗ADC设计提供了参考.

Abstract

In order to resolve the defect of comparator offset (including aperture error and static comparator offset) degrading the overall performance of high speed SHA-less pipelined ADC

an effective background digital calibration method is proposed. The detection of calibration is implemented by collecting the output residual voltage in digital domain

and the correction of calibration is implemented by controlling and configuring the DAC in analog domain. The calibration uses the difference of the mean values and the sum of extremums of the residueto characterize the aperture error and static comparator offset respectively

which avoids the disadvantages brought by other non-idealities in calibration

improves the ADC performance for high speed input

and improves the stability effectively.The proposed calibration method is applied in a 2.5 GS/s12bit ADC based on FPGA implementation. In this work

simulation and prototype verification are carried out to validate the practicability of the proposed method.The SNDR is improved by over 8dB@1.913GS/s based on the measurement. The calibration method decreases the difficulty of SHA-less pipelined ADC design

and relaxes the requirement of analog design

which provides reference for further high speed and low power ADC design.

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Keywords

references

XU W G, GAO Y F, LIU X D, et al. A 18mW 12bit 50MS/s SHA-less pipelined ADC[C]// Proceedings of the IEEE 12th IEEE International Conference on ASIC. Guiyang, China: IEEE, 2017: 776-779. DOI: 10.1109/ASICON.2017.8252591.

JU Y, LI F L, HE X J, et al. Aperture error reduction technique for subrange SAR ADC[C]// Proceedings of the 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). Vancouver, Canada: IEEE, 2016: 1-4. DOI: 10.1109/NEWCAS.2016.7604800.

JAMES D, KUNNATH A T, PURUSHOTHAMAN A, et al. Mitigating aperture error in pipelined ADCs without a front-end sample-and-hold amplifier[C]// Proceedings of the 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). Pune, India: IEEE, 2018: 7-12. DOI: 10.1109/VLSID.2018.29.

BRANDOLINI M, SHIN Y J, RAVIPRAKASH K, etal. A 5GS/s 150mW 10b SHA-less pipelined/SAR Hybrid ADC for direct-sampling systems in 28nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2015, 50(12): 2922-2934. DOI:10.1109/JSSC.2015.2464684.

ZHU C Y, LIN J, WANG Z F. Background calibration of comparator offsets in SHA-less pipelined ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(3): 357-361. DOI:10.1109/TCSII.2018.2854571.

WANG C W, WANG X, DING Y, et al. A 14 bit 250MS/s low-power pipeline ADC with aperture error eliminating technique[C]// Proceedings of 2018 IEEE International Symposium on Circuits and Systems. Florence, Italy: IEEE, 2018: 1-5. DOI: 10.1109/ISCAS.2018.8351100.

GINES A J, PERALIAS E J, RUEDA A. Fast background calibration of sampling timing skew in SHA-Less pipeline ADCs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(10): 2966-2970. DOI:10.1109/TVLSI.2017.2718625.

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