The development of advanced nano-integrated circuit processes has led to a decreasing threshold charge in microelectronic devices

resulting in an increased rate of soft errors caused by single-event effects in digital circuits. To enhance the radiation resistance of standard cells in integrated circuits

this paper proposes a NAND gate structure that is resistant to single-event transients (SETs). In the triple well process

by shorting the substrate and source of each NMOS transistor in the pull-down network

the radiation resistance of the NAND gate was effectively improved

and the hardening of the proposed NAND gate became more effective as the number of inputs increased. Particle incidence simulation experiments were performed by Sentaurus TCAD software in hybrid simulation mode. For the NMOS transistor connected to the output node

the three-dimensional physical model that has been calibrated by the process was used

and the Spice model provided by the manufacturer was adopted for other MOS transistors. Simulation results show that the proposed two-input NAND in 40 nm process could reduce the output voltage fluctuation amplitude in three-input cases at the linear energy transfer (LET) value of incidence particle of 10 MeV·cm2/mg. Besides

the effect of immunity to single particle incidence was achieved in the input mode with N2 transistor closed. For the hardened three-input NAND gate

the output voltage disturbance could be reduced by up to 85.4% even in the “worst case”. Therefore

the proposed hardening method for NAND gate has a significant effect against SET.