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A DDS circuit design with ultra-low latency and exact output frequency
更新时间:2026-10-23
    • A DDS circuit design with ultra-low latency and exact output frequency

    • Vol. 51, Issue 5, Pages: 44-49(2019)
    • DOI:10.11918/j.issn.0367-6234.201805108    

      CLC: TN492
    • Published:2019

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  • WANG Guohong, WAN Qiang, YAO Yafeng, et al. A DDS circuit design with ultra-low latency and exact output frequency[J]. 2019, 51(5): 44-49. DOI: 10.11918/j.issn.0367-6234.201805108.

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