Key circuit and algorithm design of broadband micro-power high speed dual mode AGC

GAO Yijie; ZHANG Yubin; GAN Jie; ZHAO Xu; YAO Ruilong; REN Minhua

doi:10.19304/J.ISSN1000-7180.2021.0789

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Key circuit and algorithm design of broadband micro-power high speed dual mode AGC

更新时间：2026-09-04

- Key circuit and algorithm design of broadband micro-power high speed dual mode AGC
- Vol. 39, Issue 3, Pages: 106-112(2022)
- 作者机构：
  
  北京智芯微电子科技有限公司,北京,100192
- 作者简介：
- 基金信息：
- DOI：10.19304/J.ISSN1000-7180.2021.0789
  CLC：
- Published：2022
- 稿件说明：
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高以杰, 张玉冰, 甘杰, 赵旭, 姚瑞龙, 任敏华. 宽带微功率高速双模AGC关键电路及算法设计[J]. 微电子学与计算机, 2022, 39(3): 106-112.

GAO Yijie, ZHANG Yubin, GAN Jie, et al. Key circuit and algorithm design of broadband micro-power high speed dual mode AGC[J]. 2022, 39(3): 106-112.
高以杰, 张玉冰, 甘杰, 赵旭, 姚瑞龙, 任敏华. 宽带微功率高速双模AGC关键电路及算法设计[J]. 微电子学与计算机, 2022, 39(3): 106-112. DOI： 10.19304/J.ISSN1000-7180.2021.0789.

GAO Yijie, ZHANG Yubin, GAN Jie, et al. Key circuit and algorithm design of broadband micro-power high speed dual mode AGC[J]. 2022, 39(3): 106-112. DOI： 10.19304/J.ISSN1000-7180.2021.0789.

摘要

针对宽带微功率无线通信技术(470 MHz~510 MHz)高速率、信号突发传送的特点，在设计宽带微功率射频前端芯片过程中，提出了一种去环路滤波器和去ADC的数模混合反馈型高速双模AGC设计方案(DFA-AGC)，本文对该方案的关键电路和算法进行了详细描述.为实现AGC快速响应，提出了一种新型的环路电压环路恒跨导轨到轨输入和改进型电流镜负载推挽式输出结构来提升转换速率，并设计了一种全对称差分结构的全波包络检波器来减少差分信号包络检波时间.同时，考虑到实际应用场景可能的电磁干扰，设计了一种快慢锁双模自适应切换算法以实现快锁模式下信号快速跟踪和锁定，慢锁模式下有效躲避尖峰干扰.该AGC采用SMIC 40nm CMOS工艺设计，版图尺寸约200 m×140 m.仿真结果：快锁模式下锁定和增益稳定时间小于10微秒，接收增益动态范围大于90 dB.实际测试结果，快锁模式下稳定时间约为9微秒，慢锁模式下稳定时间约为30微秒，功耗小于1 mW.

Abstract

In view of the characteristics of broadband micro-power wireless communication technology (470MHzto 510MHz) with high rate and sudden signal transmission

a digital-analog hybrid feedback and high-speed dual-mode AGC(DFA-AGC)is proposed in the process of designing broadband micro-power RF front-end chip

which removed loop filter and ADC. In order to realize the rapid response of AGC

a new type of rail-to-rail input with constanttransconductance voltage loopand an improved push-pull output structure with current mirror load areproposed to improve the conversion rate

and a full-wave envelope detector with a fully symmetric differential structure is designed to reduce the detection time of the differential signal envelope..Considering the electromagnetic interference in practical application scenarios

a fast and slow locking dual-mode adaptive switching algorithm is designed to achieve fast tracking and locking in fast locking mode

and effectively avoid peak interference in slow locking mode. The AGC is designed by SMIC 40nm CMOS process. Simulation results show that the locking and gain stabilization time is less than 10 microseconds

and the dynamic range of receiving gain is greater than 90 dB. The actual test results show thatthe stability time in fast lock mode is about 9 microseconds

and the stability time in slow lock mode is about 30 microseconds

and the power consumption is less than 1 mW.

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references

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