Research and performance optimization of five stage pipelined RISC-V processor

LI Jiemin; ZHANG Shancong

doi:10.19304/J.ISSN1000-7180.2021.0856

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Research and performance optimization of five stage pipelined RISC-V processor

更新时间：2026-09-04

- Research and performance optimization of five stage pipelined RISC-V processor
- Vol. 39, Issue 3, Pages: 78-85(2022)
- 作者机构：
  
  1. 中国科学院大学机构,北京,101408
  2. 中国科学院空间应用工程与技术中心,北京,100094
  3. 中国科学院机构太空应用重点实验室,北京,100094
- 作者简介：
- 基金信息：
- DOI：10.19304/J.ISSN1000-7180.2021.0856
  CLC：
- Published：2022
- 稿件说明：
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李介民, 张善从. 五级流水线RISC-V处理器的研究与性能优化[J]. 微电子学与计算机, 2022, 39(3): 78-85.

LI Jiemin, ZHANG Shancong. Research and performance optimization of five stage pipelined RISC-V processor[J]. 2022, 39(3): 78-85.
李介民, 张善从. 五级流水线RISC-V处理器的研究与性能优化[J]. 微电子学与计算机, 2022, 39(3): 78-85. DOI： 10.19304/J.ISSN1000-7180.2021.0856.

LI Jiemin, ZHANG Shancong. Research and performance optimization of five stage pipelined RISC-V processor[J]. 2022, 39(3): 78-85. DOI： 10.19304/J.ISSN1000-7180.2021.0856.

摘要

国内基于RISC-V指令集的嵌入式处理器的研究在近几年内得到了快速发展.在性能评估研究上多集中于2-3级流水的小规模、低功耗处理器，针对5级流水架构处理器的性能量化研究较少.针对该问题，在传统5级顺序流水架构的基础上，分别从RISC-V指令预测、流水线机制、乘除法算法、存储架构等方面分析处理器优化的策略.针对不同策略优化的处理器以AHB片上互联、APB桥接的方案实现外部模块的搭载.在FPGA上完成软硬件协同仿真验证，并在Xilinx的XC7K325T开发板上运行性能评估测试程序CoreMark，依据运行结果着重分析不同静态预测算法、不同周期乘除法运算、外挂存储的容量与设计等因素对处理器的影响.最终实现的处理器基于RV32IMZicsr架构，采用了半静态预测(资源优化)、流水线检测转发机制(处理优化)、短周期乘除法(计算优化)、最优存储架构(取指与访存优化)等性能优化策略.CoreMark跑分达到3.06 CoreMark/MHz.

Abstract

In recent years

the research of embedded processor based on RISC-V instruction set has developed rapidly in China. The research on performance evaluation is mostly focused on the small scale and low power processors with 2-3 level pipelined architectures

and there are few studies on the performance quantification of the processors with 5-level pipelined architectures. To solve this problem

based on the traditional five-level sequential pipelining architecture

the strategy of processor optimization is analyzed from the aspects of RISC-V instruction prediction

pipelining mechanism

multiplication and division algorithm

storage architecture

etc. For the processors optimized for different strategies

AHB on-chip interconnection and APB-bridge are used to carry external modules. The software and hardware co-simulation verification is completed on FPGA

and the performance evaluation test program Coremark is run on Xilinxs XC7K325T development board. According to the running results

the influences of different static prediction algorithms

different cycle multiplication and division operations

capacity and design of plug-in storage on the processor are analyzed emphatically. The final processor is based on RV32IMZicsr architecture

and adopts performance optimization strategies such as semi-static prediction (resource optimization)

pipeline detection and forwarding mechanism (processing optimization)

short-period multiplication-division method (computing optimization)

and optimal storage architecture (pointing and memory access optimization). Coremark scored 3.06 Coremark /MHz.

关键词

Keywords

references

张迅珍, 梁青, 李涛. RV32I控制单元设计与实现[J]. 微电子学与计算机, 2018, 35(3): 74-78. DOI: CNKI:SUN:WXYJ0.2018-03-019. ZHANG X Z, LIANG Q, LI T. Design and implementation of control element of RV32I[J]. Microelectronics % Computer, 2018, 35(3): 74-78. DOI: CNKI:SUN:WXYJ0.2018-03-019.

Beijing 胡振波. 手把手教你设计CPU--RISC-V处理器[M]. 北京: 人民邮电出版社, 2018: 6. DOI: 6 HU Z B. Teach you how to design CPU: RISC-V processor[M]. Beijing: People's Posts and Telecommunications Publishing House, 2018: 6. DOI: 6

Berkeley PATTERSON D, WATERMAN A. The RISC-V reader: an open architecture atlas[M]. Berkeley: University of California, 2017.

李东泽, 曹凯宁, 曲明, 等. 五级流水线RISC-V处理器软硬件协同仿真验证[J]. 吉林大学学报(信息科学版), 2017, 35(6): 612-616. DOI: 10.3969/j.issn.1671-5896.2017.06.006. LI D Z, CAO K N, QU M, et al. Hardware and software Co-simulation of RISC-V processor with five-stage pipeline[J]. Journal of Jilin University (Information Science Edition), 2017, 35(6): 612-616. DOI: 10.19292/j.cnki.jdxxp.2017.06.006.

WATERMAN A, LEE Y, PATTERSON D A, et al. The RISC-V instruction set manual, Volume Ⅰ: user-level ISA, version 2.1[R]. Berkeley: University of California, 2016.

郝振和, 焦继业, 李雨倩. 基于AHB总线的RISC-V微处理器设计与实现[J]. 计算机工程与应用, 2020, 56(20): 52-58. DOI: 10.3778/j.issn.1002-8331.1911-0331. HAO Z H, JIAO J Y, LI Y Q. Design and implementation of RISC-V microprocessor based on AHB bus[J]. Computer Engineering and Applications, 2020, 56(20): 52-58. DOI: 10.3778/j.issn.1002-8331.1911-0331.

李雨倩, 焦继业, 刘有耀, 等. 嵌入式RISC-V乱序执行处理器的研究与设计[J]. 计算机工程, 2021, 47(2): 261-267. DOI: 10.19678/j.issn.1000-3428.0057141. LI Y Q, JIAO J Y, LIU Y Y, et al. Research and design of embedded RISC-V out-of-order execution processor[J]. Computer Engineering, 2021, 47(2): 261-267. DOI: 10.19678/j.issn.1000-3428.0057141.

ASANOVIC ' K, AVIZIENIS R, WATERMAN A, et al. The rocket chip generator[R]. EECS Department, Berkeley: University of California, 2016.

雷思磊. RISC-V架构的开源处理器及SoC研究综述[J]. 单片机与嵌入式系统应用, 2017, 17(2): 56-60. DOI: CNKI:SUN:DPJY0.2017-02-019. LEI S L. Research on open source processor and SoC based on RISC-V[J]. Microcontrollers % Embedded Systems, 2017, 17(2): 56-60. DOI: CNKI:SUN:DPJY0.2017-02-019.

WATERMAN A, LEE Y, PATTERSON D A, et al. The RISC-V instruction set manual, Volume Ⅰ: user-level ISA version 2.0[R]. Berkeley: University of California, 2016.

PANG X M, YU D J, LI J B, et al. Design and application of IP core in SoC technology[C]//Proceedings of 2010 Third International Symposium on Information Science and Engineering. Shanghai, China: IEEE, 2011: 71-74. DOI: 10.1109/ISISE.2010.94.

OLUGBON A, KHAWAM S, ARSLAN T, et al. An AMBA AHB-based reconfigurable SoC architecture using multiplicity of dedicated flyby DMA blocks[C]//Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. Shanghai, China: IEEE, 2005. DOI: 10.1109/ASPDAC.2005.1466571.

李其高. 面向IoT终端设备的RISC-V微控制器设计与分析[J]. 单片机与嵌入式系统应用, 2018, 18(3): 64-66. DOI: 64 LI Q G. Design and analysis of RISC-V microcontroller for IoT endpoint devices[J]. Microcontrollers % Embedded Systems, 2018, 18(3): 64-66. DOI: 64

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