Behavioral modeling of the second-order

one-bit quantizer modulator using a method of macro-model combined with Verilog-A model is presented. The key modules of the modulator are modeled in macro-model and the functional modules are described in Verilog-A. The modules are designed and simulated in the Cadence environment based on Huahong NEC 0.25m CMOS process. The results and time of the simulation of the modules are compared with the circuits

and the SNR of the overall circuit of the modulator in both conditions are presented. The results show that this method of modeling could achieve a higher accuracy and faster simulation speed.