Because the parallel data processing and the fast carry-free algorithm can be used by using Residue Number System (RNS) in VLSI (very large scale integration) design

RNS (Residue Number System) shows the high performance

such as low power consumption

small area

and short delay

etc.According to Chinese Reminder Theorem

based on (2-1) 2 (2+1) Moduli set

the bit stream to RNS converting interface circuit is designed using Verilog language.So as to the traditional complex operation can be instead of the simple operation with parallel data with little bits.As result

complexity

delay and power consumption for single operation is reduced.The converting circuit is Σ-Δ modulated bit stream other than binary data

so it adapts to Delta-Sigma system.based DSD (Direct Stream Digital) .