In the paper the reconfigurable solution of implementation of JPEG2000 algorithm based on SOC and software/harware Cooperation is presented

and combined pipeline architecture for the 5-3 and 9-7 lifting wavelet transforms is designed.The module such as

color space transform

context formation

tier1 encoder and arithmetic encoder have been realized with our proposed architectures on FPGA to improve speed.The functions of image preprocessing

tier2 encoder and system control etc.have been finished with Nios II embeded processor software.Finally

The proposed scheme is verified with FPGA software/hardware platform based on EP3C25F672 chip of Altera Company.The experimental results of simulation with the cooperation of software and hardware show that the proposed method can effectually solve the problem about the bottleneck between coding speed and flexibility

and take the advantages both improving compression efficiency and saving chip area.