According the verification of ASICs

the traditional way to construct platform based on e language exists a problem of low verification efficiency.An improved method to build e verification components is used

in which data process is in e language components only

but verilog language is used for timing process instead.Therefore

communication frequency between Specman Elite and verilog simulator is reduced.An experiment of SDH processing chip verification proves the simulation time of test case decreased by 50% to 70% comparing with the traditional one.