Non-blocking instruction Cache is one Cache that can continue to provide instruction and data

when waiting for the prefetch data.In this paper

first analyze the processors demand for multithreading non-blocking cache

then put forward the timing request and the functional structure.SystemVerilog is employed to build up the simulation model of the proposed architecture and the performace evaluation.Evaluation results show that the architecture can be applied to the design of fetch engine in multithreading or out of order execution processors.