Based on the four dynamic threshold voltage NMOS transistor and two active resisitor

a novel 1.2V low power analog multiplier is prensnted in CSMC 0.6m DPDM CMOS process.The number of input transistor has been decreased and the biased transistor and circuits have been saved.When the 5MHz input signal V with 1.0V peak-to-peak amplitude and the 100MHz input signal V with 0.5V peak-to-peak amplitude

the peak-to-peak amplitude of output signal V is about 350mV.The margin between the first order harmonious wave and the third order harmonious wave of the output wave is about 40dB.The frequency bandwidth of the 1.2V CMOS analog multiplier is 375MHz

and the average power supply current is 30A.It is fit for portable electronic product and below 400MHz bandwidth field.