Coherent demodulation has excellent noise immunity and error performance

widely used in the all--digital receiver. Carrier synchronization and bit synchronization are the key technologies directly affecting the demodulation performance. Take QPSK signal for example

this paper uses evolutionary costas loop to achieve carrier synchronization

and PLL structure based on digital interpolation and Gardner algorithm to recover timing clock. From the perspective of project application

some key points of hardware implementation are discussed in detail. The feasibility and correctness of this design are verified on a low--cost Field Programmable Gate Array (FPGA) chip

the demodulator has good anti-- noise

high-- speed and real-- time performance

with great reference value of engineering.