In this paper

a novel design and hardware implementation using parallel computing for 2-D integer lifting wavelet transform (IWT) is proposed of which input datas are divided into groups

its row and column transform module use parallel computing technology.This design is capable to produce 2 results every cycle

which takes N/2 time units to finish a N×N 2D IWT.And also

we implemented it in FPGA

the estimated frequency of operation is 394.415MHz.