High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC.Differing from previous video codec standards

HEVC proposes the variable block size Transform Unit (TU) to conduct spatial redundancy compression.In this paper

a novel fully pipelined 2 -D 32×32 IDCT architecture based on HEVC is presented.To reduce the I/O peak bandwidth and hardware overhead

single -port I/O

the butterfly unrolling and the Odd/Even accumulation separation method is adopted.Using TSMC90nm technology

the proposed architecture is implemented with the maximum work frequency at 315M Hz with 47K Gates.Simulation results show that the proposed architecture is able to process 4096×2048@30fps image with 32×32 IDCT.