To meet the demand for low power

low-cost and miniaturization of the medical system-on-chip(SOC)

a AHB bus compatible Nor Flash controller IP was designed.The optimal design methods of simplifying the sector erase module

increasing the write data register and hardware unlock were adopted to overcome the disadvantageous of conventional Flash controller

such as the complicated logical design

long waiting time for reading and writing.The design was verified by FPGA and taped out finally

the verified results show that the function of the IP was correct and the bus utilization has been improved.When the system ran at 10MHz and the S29LV008J chip was selected

the bus utilization time was reduced 165s when sixteen 32 bit data were stored continuously.