With the development of System--on--chip designs

more and more functionality is integrated into a single chip. The complexity of the system on a chip demands a higher requirement of onchip interconnect bandwidth and reliability. The driver pre-- emphasis architecture based on transmitter equalization techniques can effectively improve the interconnect channel bandwidth and eliminate inter--symbol interference hy emphasizing the high--frequency components while attenuating low--frequency components. The delay in pre--emphasis circuit structure has a significant impact on circuit performance. In this paper

we analyze the existence of optimal delay which is related to the RC parameter of the channel by means of Laplace transform. The result of spice simulation show that the optimized pre- emphasis circuit can improve the transmission bandwidth more effectively

thus achieving high--speed on--chip data transmission.