The deep submicron technology presents lots of challenges to the physical design of VLSI

the key to timing closure is the interconnect delay and crosstalk. A method based on re-synthesis

region constraints and crosstalk prevent is presented to resolved the timing closure problem of physical design in the paper.The method is verified by design a 5.3 million gate multi-core DSP chip in 65nm technology.The design example demonstrate that the method efficiently solves the interconnect delay and crosstalk

and achieves timing closure.