As the traditional node localization method was mainly used for two-dimensional plane node

presented a hardware implementation of particle filter for spatial node localization. For the problem of large amount of computation and low degree of parallelism

optimized particle filter algorithm. Proposed a hardware architecture that made the computing speed higher

and decreased resource consumption. Pipelining architecture was carried out through SystemC language

bringing to further improvement of the design efficiency. The experimental study on FPGA indicated that the proposed particle filters algorithm has good positioning accuracy. Hardware consuming was 6 826 logic cells

and the average execution time was reduced by about 1/3.