In this paper

we analysis several bottom processing algorithms on target recongnition and propose spatial filtering calculation model

and implement a set of real-time hardware architecture for spatial filtering algorithms with VerilogHDL.The advantage of this structure is that it has a good configurability which can make users to choose proper filtering methods and calculated parameters according their needs.At present

we have completed digital IC front-end design process of the module

such as the structure design

RTL coding

function verification

etc.Simultaneously

we completed the work of Circuit synthesis and formality verification with Design Compiler Under the SMIC 0.18m CMOS process

and obtained the area and power are 1.9mm equal to 114.2kGates

30 mW respectively at the frequency of 120 MHz.The design has fast speed

low-power

highly configurable advantages compared with the published similar designs.