This paper deals with a high-speed in-line packet transceiver structure design for the 10 Gb/s Ethernet.By adopting a shared and distributed two-stage buffering mechanism

the high-speed packet transfer is achieved real-time.The high-efficient scheduling to the changeable length packets is realized by improving hardware implementation of a scheduling algorithm.The packet transceiver is modeled with the aid of systemC at transaction level.By simulating and optimizing the number of the distributed FIFO buffers

the packet loss rate drop to zero.The design is implemented and simulated at RTL level.To verify the design

it is used in a 10 Gb/s in-line network security processor and simulated.The simulation shows that the system can achieve 10.06 Gb/s throughput at the clock rate 250 M Hz without packets loss

this verified the performance of the design.The design can be used in the next generation 40/100 Gb/s Ethernet to protect the information security through configure the number of the distributed FIFO buffers.