Design of a digital decimation filter for UHF RFID Σ-Δ ADC in 0.18μm CMOS process

and complete the entire process

including pre and post-simulation

logic synthesis

floorplan

and layout design

etc. The filter use comb filter

compensation filter and half-band filter cascade to achieve filtering and down-sampling. Rational choice of archi- tecture and order and the optimal of coefficient with CSD coding.With sampling frequency of 64 MHz

and oversampling ratio of 32

simulation results showed that by processing the bit stream from a 2-order Σ-Δ modulator

a signal- to- noise distortion ratio (SNDR) of 53.8 dB is obtained for the filter. In the operating voltage of 1.8 V

the power consumption is 15 mW

layout area 0.45 mm×0.45 mm

and can meet the demand of RFID Σ-Δ ADC.