The newest international video coding standard HEVC (High Efficiency Video Coding) is published by ITU-T and ISO/IEC in January

2013.To improve the compression efficiency

some new technologies have been adopted in HEVC.In spatial transform aspect

HEVC supports variable transform block sizes from 4×4 to 32×32 for IDCT as well as mode dependent 4×4IDST.In this paper

a novel IDCT/IDST architecture for HEVC is proposed.It uses pipelined data flow scheduling and coefficient matrix optimization to improve hardware efficiency and bandwidth utilization.Synthesized with 65 nm technology

the 1DIDCT/IDST is 40 K gate count and the maximum working frequency is 500 MHz.Compared with previous work

our architecture can get more than 30% reduction in hardware cost and 60% improvement in throughput efficiency.Experimental results show that it can deal with IDCT/IDST for 4k×2k@30f/s video sequence.