Motion compensation plays an important role in the H.264/AVC video coding standard

the fractional pixel motion compensation is one of the most complicated part.So it is especially important to improve the fractional pixel operation time

reduce the complexity of the algorithm.In this paper

the original fractional pixel interpolation algorithm is improved

the traditional six tap FIR filter is changed to the fourth tap FIR filter to calculate half pixel

and pipeline structure is used for FPGA design

so the hardware can handle 12 pixels one time.The architecture is described in Verilog and synthesized into the Xilinx Virtex6 FPGA device.The simulation results show that the proposed half pixel interpolation algorithm can be operated at the frequency of 213 MHz

with clock recycles are reduced to 36.At the same time

the hardware complexity is reduced obviously.