3D-TCAD simulations in a 0.18m process are used to show the effect of gate shapes on the single event transients of both PMOS and NMOS.The result turn out that the SET pulse widths of enclosed layout transistors are much smaller than the standard layout transistors.The mechanisms and process that affect the charge collection in both PMOS and NMOS of different layout structures are studied.And suggestions are made towards design guidelines and hardening approaches.