In order to reduce the waiting time of the multiplication instructions in reservation

a 32-bit pipelined multiplier is designed in this paper.It will be applied to the design of a superscalar processor.In this design

a modified booth encoder is used and partial product generator circuit is optimized.The partial product is compressed by the combination with 4-2 compressor and 3-2 compressor in Wallace tree structure.At last

pipeline registers are inserted according to the delay of the several levels

which will accelerate computing speed.The multiplier is synthesized in GSMC 0.18μm process.According to simulation and verification

this multiplier reduce the complement time of the IR waiting to execute in reservation stations.A new multiplication is sent to multiplier to compute in every cycle.