To reduce the average branch penalty

the average memory reference latency and the program code size in VLIW(Very Long Instruction Word) architecture

A new method to implement branch prediction and value prediction in VLIW is presented. Firstly

the confliction of the dynamic prediction in Superscalar and the static instruction parallelism in VLIW is analyzed. Then the branch and load instruction is expanded

one-to-one correspondence between the delay slot and the new expanded instructions. The pipeline is stalled and the write back stage is delayed according to the given instruction. Benchmark tests based on Gem5 and Magnolia VLIW DSP of Tsinghua University are presented to prove the advantage of the branch prediction and value prediction in VLIW.