A novel wire-length driven placement algorithm for antifuse FPGA is proposed based on the characteristics of the antifuse FPGA architecture. The proposed algorithm is based on the simulated annealing algorithm of VPR and takes the limited vertical routing resources of the antifuse FPGA into account. A new cost function is proposed and the algorithm is implemented on a CAD platform. The experimental results showed that compared to the placement results of VPR

the proposed algorithm not only improves the total wire length by 12% on average

but also reduces the number of programmed horizontal antifuses.