The single event effect sensitivity of different circuit nodes in the ferroelectric memory cell is studied by circuit simulation

and the single event upset mechanism of the ferroelectric memory cell is analyzed. The simulation results show that the upset of the ferroelectric memory cell depends on the polarization state of the ferroelectric capacitor. When a high energy particle strikes the off-state NMOS in the memory array

the polarization reversal only happens to the corresponding ferroelectric capacitor which stored data "0". Based on the readout methods of the 2T2C and 1T1C ferroelectric memory cell

the upset types of the output data are analyzed. Some methods to harden the FRAM cell against SEU are also proposed.