To solve the problem of SpaceWire performance degradation

which is caused by the current SpaceWire flow control mechanism when SpaceWire interface transfers the bulk data

a Two-Level memory structure is proposed. The current applications and the existing problems about SpaceWire are introduced. By analyzing the flow control mechanism of the SpaceWire and the factors impacting the bus efficiency and the whole system performance

a Two-Level memory structure

which ensures the first level memory have sufficient space to receive or transfer the bulk data

is proposed.Based on SpaceWire protocol and the Two-Level memory structure

a SpaceWire node IP Core is designed

which can effectively control bulk data transfer through hardware prefetching. Finally

while the IP Core is integrated with the LEON3-FT processor

system level simulation and testing are carried out. The results show that

compared with the conventional SpaceWire node

this design can improve 62.7 times in bus efficiency

and at least14.5 times in system processing data efficiency when it transfers the bulk data.