基于子树重构的三维时钟树拓扑结构优化

钱晨; 王琴; 谢憬; 毛志刚

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基于子树重构的三维时钟树拓扑结构优化

更新时间：2026-09-04

- 基于子树重构的三维时钟树拓扑结构优化
- Clock Tree Topology Optimization Based on Reconstructing Subtree Topology for 3D Ics
- 微电子学与计算机 2016年33卷第5期页码：10-14
- 作者机构：
  
  上海交通大学微纳电子学系,上海,200240
- 作者简介：
- 基金信息：
  
  国家自然科学基金项目 61176037
- DOI：
  中图分类号：
- 纸质出版：2016
- 稿件说明：
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钱晨, 王琴, 谢憬, 毛志刚. 基于子树重构的三维时钟树拓扑结构优化[J]. 微电子学与计算机, 2016, 33(5): 10-14.

QIAN Chen, WANG Qin, XIE Jing, et al. Clock Tree Topology Optimization Based on Reconstructing Subtree Topology for 3D Ics[J]. 2016, 33(5): 10-14.
钱晨, 王琴, 谢憬, 毛志刚. 基于子树重构的三维时钟树拓扑结构优化[J]. 微电子学与计算机, 2016, 33(5): 10-14. DOI：

QIAN Chen, WANG Qin, XIE Jing, et al. Clock Tree Topology Optimization Based on Reconstructing Subtree Topology for 3D Ics[J]. 2016, 33(5): 10-14. DOI：

摘要

传统的基于TSV的三维集成电路时钟树综合流程主要包括抽象拓扑树生成、层嵌入、布线和缓冲器插入.现有的三维时钟抽象拓扑树生成算法大多忽视了对由经典时钟拓扑树生成算法得到的抽象树结构的优化调整.对此提出了一种3D抽象拓扑树优化算法

能够调整特定子树的根节点位置从而优化抽象拓扑树结构.同时

把该优化算法整合到传统的时钟树综合流程中.仿真实验结果表明优化算法可以将三维集成电路时钟网络的总线长减小最多4.56%

而时钟延迟最多可减少14.67%.

Abstract

The traditional TSV-based 3D clock tree synthesis (3D CTS) flow mainly concludes abstract topology generation

embedding

routing and buffering. The classic 3D clock tree abstract topology generation algorithms ignore the adjustment for the generated topology after the first step. In this paper

we propose a clock tree topology optimization algorithm

the LMOR algorithm

for reconstructing the structure of some specific subtrees in the generated 3D clock tree abstract topology and relocating the position of the roots of these subtrees. The simulation results show that the total wirelength and delay can be reduced by up to 4.56% and 14.67%.

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references

Pan X, Xie J, Wang Q, et al. Noise aware clock tree synthesis for 3D ICs[C]//Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on. China, Guilin, IEEE, 2014: 1-3.

Zhao X, Minz J, Lim S K. Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs[J]. Components, Packaging and Manufacturing Technology, 2011, 1(2): 247-259. DOI: 247

Jackson M A B, Srinivasan A, Kuh E S. Clock routing for high-performance ICs[C]//Design Automation Conference, 1990. Proceedings. 27th ACM/IEEE. USA, Califonia, IEEE, 1990: 573-579.

Edahiro M. A clustering-based optimization algorithm in zero-skew routings[C]//Proceedings of the 30th international Design Automation Conference. New York, ACM, 1993: 612-616.

Minz J, Zhao X, Lim S K. Buffered clock tree synthesis for 3D ICs under thermal variations[C]//Proceedings of the 2008 Asia and South Pacific Design Automation Conference. Soul, IEEE Computer Society Press, 2008: 504-509.

Kim T Y, Kim T. Clock tree synthesis for TSV-based 3D IC designs[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2011, 16(4): 11-21. DOI: 11

Kim T Y, Kim T. Clock tree embedding for 3D ICs[C]//Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific. Taiwan, Taipei, IEEE, 2010: 486-491.

Zhao X, Lim S K. Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs[C]//Proceedings of the 2010 Asia and South Pacific Design Automation Conference. Macao, IEEE Press, 2010: 175-180.

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