The process of SM3 algorithm is introduced in detail

and the hardware of the control flow and the data flow are designed. In the design of the control flow

the design of state-machine is analyzed in this paper emphatically in the process of message filling. In the design of the data flow

a new structure of adder called Two Parallel Road Adder is put forward. Combined the application of CSA structure

the clock delay of the critical path has been optimized greatly and at last this paper finish high speed ASIC design of SM3 algorithm. Compiling under the 65 nm technology library

data throughput can reach 3.37 GB/s. The design proposed in this paper could meet the need of fast and efficient message abstract generating.