1. 中国科学院 机构 微电子研究所,北京,100029
2. 新一代通信射频芯片技术北京市重点实验室,北京,100029
纸质出版:2016
移动端阅览
柯强, 卫宝跃, 梁帅, 刘昱, 张海英. 一种基于反相器的音频应用低功耗Sigma-Delta模数转换器[J]. 微电子学与计算机, 2016, 33(8): 24-28.
KE Qiang, WEI Bao-yue, LIANG Shuai, et al. A Low Power Inverter-Based Sigma-Delta ADC for Audio Applications[J]. 2016, 33(8): 24-28.
为实现音频应用低功耗Sigma-Delta模数转换器的设计
采用基于反相器的设计方法.模数转换器中Sigma-Delta调制器采用单环三阶前馈结构
以及基于反相器的开关电容积分器设计
并采用恒定跨导偏置LDO精确调整反相器的工作点
提高电路稳定性.该Sigma-Delta调制器采用SMIC 0.18 μm CMOS工艺
在采样频率6.144 MHz下
24 kHz音频信号带宽内
信噪失真比(SNDR)为91.5 dB
动态范围(DR)为96 dB
工作电源电压为1.3 V
整体功耗为0.48 mW
满足高性能低功耗的要求.
An inverter-based design technique is applied to accomplish a low power Sigma-Delta analog-to-digital converter (ADC) for audio applications. The Sigma-Delta modulator of the ADC adopts three order feedforward structure. The modulator is based on inverter-based switched-capacitor integrator. To increase the robust of the modulator
a constant gm bias LDO is used to regulate the inverter bias point. The Sigma-Delta modulator is implemented in SMIC 0.18 μm CMOS process. The simulation results of the Sigma-Delta modulator achieve 91.5 dB signal to noise and distortion ratio (SNDR)
96 dB dynamic range (DR) over 24 kHz audio band with 6.144 MHz sampling frequency and it consumes 0.48 mW power with 1.3 V supply voltage. The modulator is suitable for high performance and low power applications.
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李迪. 高性能sigma-delta ADC的设计与研究[D]. 西安: 西安电子科技大学, 2010.
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