As the complexity and size of SOC(System on chip)grow

verification of design faces huge challenge. There are many defects in the traditional verification so that it cant meet the demand of manufacture in the aspect of efficiency. UVM is a universal verification methodology which springs up in recent years and has high efficiency. It can not only shorten the period of verification

but also can be reused conveniently. The reuse of UVM mainly includes Horizontal reuse and Vertical reuse. This paper focuses on the Vertical reuse and takes the APB bus as example

to expatiate how to build a verification platform from module level to system level. The methodology obviously shows that the Vertical reuse has the advantage of improving verification efficiency.